Applied the series. Thanks! Alex
On Mon, Aug 3, 2026 at 11:13 AM Timur Kristóf <[email protected]> wrote: > > Set bits on dword 2 like GFX7-8 except load_global_uconfig > which doesn't exist on GFX6. > > Emit VS_PARTIAL_FLUSH before VGT_FLUSH like GFX7-8. > > For reference see old PAL which explains the bit fields in > this register and that load_global_uconfig doesn't exist on GFX6 > and also see gfx_v7_ring_emit_cntxcntl() for the GFX7 code > which this commit follows. > > Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si > v8") > Signed-off-by: Timur Kristóf <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 28 ++++++++++++++++++++------- > 1 file changed, 21 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > index cd2a14ecdba8..0cbaae73a0bf 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > @@ -1882,11 +1882,13 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring > *ring) > return r; > } > > -static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) > +static void gfx_v6_0_ring_emit_event_write(struct amdgpu_ring *ring, > + uint32_t event_type, > + uint32_t event_index) > { > amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); > - amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | > - EVENT_INDEX(0)); > + amdgpu_ring_write(ring, EVENT_TYPE(event_type) | > + EVENT_INDEX(event_index)); > } > > static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, > @@ -2997,10 +2999,22 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct > amdgpu_device *adev) > > static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t > flags) > { > - if (flags & AMDGPU_HAVE_CTX_SWITCH) > - gfx_v6_0_ring_emit_vgt_flush(ring); > + u32 dw2 = 0x80000000; /* set load_enable otherwise this package is > just NOPs */ > + > + if (flags & AMDGPU_HAVE_CTX_SWITCH) { > + gfx_v6_0_ring_emit_event_write(ring, VS_PARTIAL_FLUSH, 4); > + gfx_v6_0_ring_emit_event_write(ring, VGT_FLUSH, 0); > + > + /* set load_global_config (load_global_uconfig doesn't exist > on GFX6) */ > + dw2 |= 0x1; > + /* set load_cs_sh_regs */ > + dw2 |= 0x01000000; > + /* set load_per_context_state & load_gfx_sh_regs */ > + dw2 |= 0x10002; > + } > + > amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); > - amdgpu_ring_write(ring, 0x80000000); > + amdgpu_ring_write(ring, dw2); > amdgpu_ring_write(ring, 0); > } > > @@ -3527,7 +3541,7 @@ static const struct amdgpu_ring_funcs > gfx_v6_0_ring_funcs_gfx = { > 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, > vm fence */ > 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ > SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* > gfx_v6_0_ring_emit_vm_flush */ > - 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */ > + 3 + 2 + 2 + /* gfx_v6_ring_emit_cntxcntl including VGT flush > */ > 5, /* SURFACE_SYNC */ > .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ > .emit_ib = gfx_v6_0_ring_emit_ib, > -- > 2.55.0 >
