On Mon, Aug 10, 2026 at 5:55 AM David Rosca <[email protected]> wrote: > > After a recent change VCE now hangs when VCE_CMD_END is emitted > after a pipeline sync without VM flush. > Implement insert_end to correctly insert only one VCE_CMD_END per job. > > Fixes: 83a8dee2bdfb ("drm/amdgpu: always emit the job vm fence") > Signed-off-by: David Rosca <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 26 ++++++++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > index 9f4e88440c0a..a9497e2e07f7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > @@ -809,6 +809,23 @@ static void vce_v3_0_ring_emit_ib(struct amdgpu_ring > *ring, > amdgpu_ring_write(ring, ib->length_dw); > } > > +static void vce_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, > + u64 seq, unsigned flags) > +{ > + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); > + > + amdgpu_ring_write(ring, VCE_CMD_FENCE); > + amdgpu_ring_write(ring, addr); > + amdgpu_ring_write(ring, upper_32_bits(addr)); > + amdgpu_ring_write(ring, seq); > + amdgpu_ring_write(ring, VCE_CMD_TRAP); > +} > + > +static void vce_v3_0_ring_insert_end(struct amdgpu_ring *ring) > +{ > + amdgpu_ring_write(ring, VCE_CMD_END); > +} > + > static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring, > unsigned int vmid, uint64_t pd_addr) > { > @@ -818,7 +835,6 @@ static void vce_v3_0_emit_vm_flush(struct amdgpu_ring > *ring, > > amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); > amdgpu_ring_write(ring, vmid); > - amdgpu_ring_write(ring, VCE_CMD_END); > } > > static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring) > @@ -884,17 +900,19 @@ static const struct amdgpu_ring_funcs > vce_v3_0_ring_vm_funcs = { > .set_wptr = vce_v3_0_ring_set_wptr, > .patch_cs_in_place = amdgpu_vce_ring_parse_cs_vm, > .emit_frame_size = > - 6 + /* vce_v3_0_emit_vm_flush */ > + 5 + /* vce_v3_0_emit_vm_flush */ > 4 + /* vce_v3_0_emit_pipeline_sync */ > - 6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */ > + 5 + 5 + /* vce_v3_0_ring_emit_fence x2 vm fence */ > + 1, /* vce_v3_0_ring_insert_end */ > .emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */ > .emit_ib = vce_v3_0_ring_emit_ib, > .emit_vm_flush = vce_v3_0_emit_vm_flush, > .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync, > - .emit_fence = amdgpu_vce_ring_emit_fence, > + .emit_fence = vce_v3_0_ring_emit_fence, > .test_ring = amdgpu_vce_ring_test_ring, > .test_ib = amdgpu_vce_ring_test_ib, > .insert_nop = amdgpu_ring_insert_nop, > + .insert_end = vce_v3_0_ring_insert_end, > .pad_ib = amdgpu_ring_generic_pad_ib, > .begin_use = amdgpu_vce_ring_begin_use, > .end_use = amdgpu_vce_ring_end_use, > -- > 2.43.0 >
