On 26-08-2026 11:34 pm, Deucher, Alexander wrote:
AMD General
-----Original Message-----
From: Sunil Khatri <[email protected]>
Sent: Wednesday, August 26, 2026 1:59 PM
To: Deucher, Alexander <[email protected]>; Koenig, Christian
<[email protected]>
Cc: [email protected]; Khatri, Sunil <[email protected]>
Subject: [PATCH v2 1/2] drm/amdgpu/userq: use fence_val instead or rptr
rptr is a confusing variable name as it is a fence value written by the cp in
the
fence address and no where related to the rptr.
For a little history, the fence value is the actually wptr written by the
application when it submits the protected fence packet. The firmware writes
the rptr that is aligned to that wptr as the fence value. But in this case, I
agree that it is confusing, especially for someone without the history.
Patches are:
Reviewed-by: Alex Deucher <[email protected]>
Totally agree with that. I knew its the wptr value that is written in
the fence address but i was confused so many times while debugging the
sdma issue.
Thanks for the quick review on these.
Regards
Sunil Khatri
Signed-off-by: Sunil Khatri <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
index 09e2079cfdbd..e862b65f5366 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
@@ -148,13 +148,13 @@ amdgpu_userq_fence_driver_process(struct
amdgpu_userq_fence_driver *fence_drv)
LIST_HEAD(to_be_signaled);
struct dma_fence *fence;
unsigned long flags;
- u64 rptr;
+ u64 fence_val;
spin_lock_irqsave(&fence_drv->fence_list_lock, flags);
- rptr = amdgpu_userq_fence_read(fence_drv);
+ fence_val = amdgpu_userq_fence_read(fence_drv);
list_for_each_entry(userq_fence, &fence_drv->fences, link) {
- if (rptr < userq_fence->base.seqno)
+ if (fence_val < userq_fence->base.seqno)
break;
}
--
2.34.1
