On 2026-08-27 11:19, Fangzhi Zuo wrote:
> FRL (Fixed Rate Link) was gated behind the DC_FRL_MASK feature flag,
> leaving it disabled unless a user explicitly opted in via the
> amdgpu.dcfeaturemask module parameter.
>
> Invert the DC_FRL_MASK check so init_data.flags.enable_frl defaults to
> true, and repurpose the mask bit as an opt-out for users who need to
> fall back to TMDS-only signalling. Update the DC_FEATURE_MASK
> documentation accordingly.
>
> Signed-off-by: Fangzhi Zuo <[email protected]>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index a27c1fa74994..bf5369cc8b13 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -555,7 +555,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
> init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 =
> true;
>
> - if (amdgpu_dc_feature_mask & DC_FRL_MASK)
> + /* FRL is enabled by default; DC_FRL_MASK can be set to opt out. */
> + if (!(amdgpu_dc_feature_mask & DC_FRL_MASK))
> init_data.flags.enable_frl = true;
>
> init_data.flags.seamless_boot_edp_requested = false;
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
> b/drivers/gpu/drm/amd/include/amd_shared.h
> index e3baef809cd1..87eea3360450 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -287,7 +287,7 @@ enum DC_FEATURE_MASK {
> */
> DC_REPLAY_MASK = (1 << 9),
> /**
> - * @DC_FRL_MASK: (0x400) disabled by default
> + * @DC_FRL_MASK: (0x400) enabled by default; set to disable FRL
I think it'd be better if we don't redefine what this mask means.
I think this would be better:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 53738b40c97f..9c2ff3e147d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -218,8 +218,9 @@ int amdgpu_smu_pptable_id = -1;
* DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
* PSR (bit 3) disabled by default
* EDP NO POWER SEQUENCING (bit 4) disabled by default
+ * FRL (bit 10) enabled by default
*/
-uint amdgpu_dc_feature_mask = 2;
+uint amdgpu_dc_feature_mask = DC_MULTI_MON_PP_MCLK_SWITCH_MASK | DC_FRL_MASK;
uint amdgpu_dc_debug_mask;
uint amdgpu_dc_visual_confirm;
int amdgpu_async_gfx_ring = 1;
Harry
> */
> DC_FRL_MASK = (1 << 10),
> };