On 2026-08-27 11:54, Fangzhi Zuo wrote:
> FRL (Fixed Rate Link) is required to drive HDMI 2.1 high-bandwidth
> modes and is broadly supported on capable sinks, but it was left
> disabled unless a user explicitly opted in via the
> amdgpu.dcfeaturemask module parameter.
>
> Enable it by default by adding DC_FRL_MASK to the default
> amdgpu_dc_feature_mask value, keeping the mask semantics unchanged.
>
> Signed-off-by: Fangzhi Zuo <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Harry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
> drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 53738b40c97f..9c2ff3e147d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -218,8 +218,9 @@ int amdgpu_smu_pptable_id = -1;
> * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
> * PSR (bit 3) disabled by default
> * EDP NO POWER SEQUENCING (bit 4) disabled by default
> + * FRL (bit 10) enabled by default
> */
> -uint amdgpu_dc_feature_mask = 2;
> +uint amdgpu_dc_feature_mask = DC_MULTI_MON_PP_MCLK_SWITCH_MASK | DC_FRL_MASK;
> uint amdgpu_dc_debug_mask;
> uint amdgpu_dc_visual_confirm;
> int amdgpu_async_gfx_ring = 1;
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
> b/drivers/gpu/drm/amd/include/amd_shared.h
> index e3baef809cd1..7e29fe312ac6 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -287,7 +287,7 @@ enum DC_FEATURE_MASK {
> */
> DC_REPLAY_MASK = (1 << 9),
> /**
> - * @DC_FRL_MASK: (0x400) disabled by default
> + * @DC_FRL_MASK: (0x400) enabled by default
> */
> DC_FRL_MASK = (1 << 10),
> };
