On 8/27/26 17:48, Sunil Khatri wrote: > update the kernel docs for amdgpu_userq_fence_read_wptr. > > Signed-off-by: Sunil Khatri <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c > index 5b936d12c55b..c270635c907b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c > @@ -361,7 +361,7 @@ static const struct dma_fence_ops amdgpu_userq_fence_ops > = { > * > * Read the wptr value from userq's MQD. The userq signal IOCTL > * creates a dma_fence for the shared buffers that expects the > - * RPTR value written to seq64 memory >= WPTR. > + * fence_val written to seq64 fence address >= WPTR.
Mhm, that isn't ideal either. Maybe use something like this: Read the wptr value from userq's MQD. This value will become the rptr when the HW executes the commands and written it to the seq64 memory. This way the wptr can be used a seq_no to create a dma_fence. Regards, Christian. > * > * Returns wptr value on success, error on failure. > */
