From: Lijo Lazar <[email protected]> Add handlers for ualink notifications from ASP. Pause/Resume notifications are not handled currently.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 64 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h | 3 + drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 34 ++++++++++-- drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c | 48 +++++++++++++++- 4 files changed, 143 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c index 5efee75faddb2..de79b2ea1f99a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c @@ -204,6 +204,70 @@ static int amdgpu_ualink_query_info(struct amdgpu_device *adev) return 0; } +int amdgpu_ualink_config_update_handler(struct amdgpu_device *adev) +{ + int r; + u32 status = 0; + + /* TBD: Stop ASP interrupts if driver faced an issue */ + if (adev->ualink.mgr_state != AMDGPU_UALINK_INIT_COMPLETE) { + dev_dbg(adev->dev, + "UALink not initialized, skipping config update\n"); + status = !!(adev->ualink.mgr_state == AMDGPU_UALINK_INIT_ERROR); + goto out; + } + + /*TBD: find the right value of status to be sent to ASP*/ + r = amdgpu_ualink_query_info(adev); + if (r) { + dev_info(adev->dev, "UALink config update failed %d\n", r); + status = 1; + } + +out: + return psp_ual_send_completion(&adev->psp, adev->ualink.psp_if_ver, + PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE_ID, + status); +} + +int amdgpu_ualink_pause_handler(struct amdgpu_device *adev) +{ + u32 status = 0; + + if (adev->ualink.mgr_state != AMDGPU_UALINK_INIT_COMPLETE) { + dev_dbg(adev->dev, + "UALink not initialized, skipping pause update\n"); + status = !!(adev->ualink.mgr_state == AMDGPU_UALINK_INIT_ERROR); + goto out; + } + + dev_dbg(adev->dev, "UALink pause command is not handled\n"); + +out: + return psp_ual_send_completion(&adev->psp, adev->ualink.psp_if_ver, + PSP_GFX_INT_CTXT_UAL_CMD_PAUSE_ID, + status); +} + +int amdgpu_ualink_resume_handler(struct amdgpu_device *adev) +{ + u32 status = 0; + + if (adev->ualink.mgr_state != AMDGPU_UALINK_INIT_COMPLETE) { + dev_dbg(adev->dev, + "UALink not initialized, skipping pause update\n"); + status = !!(adev->ualink.mgr_state == AMDGPU_UALINK_INIT_ERROR); + goto out; + } + + dev_dbg(adev->dev, "UALink resume command is not handled\n"); + +out: + return psp_ual_send_completion(&adev->psp, adev->ualink.psp_if_ver, + PSP_GFX_INT_CTXT_UAL_CMD_RESUME_ID, + status); +} + int ualink_ip_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h index 6f522bcafa442..ce8b643811dfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h @@ -391,6 +391,9 @@ void amdgpu_ualink_sw_fini(struct amdgpu_device *adev); int ualink_send_hello(struct amdgpu_device *adev, u32 remote_accel_id); +int amdgpu_ualink_config_update_handler(struct amdgpu_device *adev); +int amdgpu_ualink_pause_handler(struct amdgpu_device *adev); +int amdgpu_ualink_resume_handler(struct amdgpu_device *adev); int amdgpu_ualink_sysfs_init(struct amdgpu_device *adev); void amdgpu_ualink_sysfs_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 77be21c3eada3..0803cfc445dc7 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -400,11 +400,35 @@ struct psp_gfx_cmd_req_perf_hw { #define PSP_GFX_UAL_MAX_STATIONS_V1 64 /* max UALink stations */ #define PSP_GFX_UAL_MAX_ACC_BIT_MASK 32 /* max accelerator bit mask 32*32 */ -enum psp_gfx_ual_npa_address_mode -{ - PSP_GFX_UAL_NPA_ADDRESS_MODE_SOURCE_ALIASING = 0, - PSP_GFX_UAL_NPA_ADDRESS_MODE_SOURCE_IDENTIFICATION = 1, - PSP_GFX_UAL_NPA_ADDRESS_MODE_MAX +/* Interrupt category identifiers (upper byte) - ASP interrupts to Driver */ + +/* Commands from ASP */ +#define PSP_GFX_INT_CTXT_UAL_CAT_CMD 0x01000000 +/* Mask for Command bits */ +#define PSP_GFX_INT_CTXT_UAL_CAT_CMD_MASK 0x000000FF +/* Notifications from ASP */ +#define PSP_GFX_INT_CTXT_UAL_CAT_NOTIFY 0x02000000 +/* Mask for category bits */ +#define PSP_GFX_INT_CTXT_UAL_CAT_MASK 0xFF000000 + +#define PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE_ID 0x00000001 +#define PSP_GFX_INT_CTXT_UAL_CMD_PAUSE_ID 0x00000002 +#define PSP_GFX_INT_CTXT_UAL_CMD_RESUME_ID 0x00000003 + +/* Command interrupts from ASP (GIM must execute action) */ +#define PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE \ + (PSP_GFX_INT_CTXT_UAL_CAT_CMD | PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE_ID) + +#define PSP_GFX_INT_CTXT_UAL_CMD_PAUSE \ + (PSP_GFX_INT_CTXT_UAL_CAT_CMD | PSP_GFX_INT_CTXT_UAL_CMD_PAUSE_ID) + +#define PSP_GFX_INT_CTXT_UAL_CMD_RESUME \ + (PSP_GFX_INT_CTXT_UAL_CAT_CMD | PSP_GFX_INT_CTXT_UAL_CMD_RESUME_ID) + +enum psp_gfx_ual_npa_address_mode { + PSP_GFX_UAL_NPA_ADDRESS_MODE_SOURCE_ALIASING = 0, + PSP_GFX_UAL_NPA_ADDRESS_MODE_SOURCE_IDENTIFICATION = 1, + PSP_GFX_UAL_NPA_ADDRESS_MODE_MAX }; enum psp_gfx_ual_ports_per_station diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c index 85857b747bd46..dcfc9be269b07 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c @@ -428,6 +428,48 @@ static const struct amdgpu_irq_src_funcs psp_v15_0_8_irq_funcs = { .process = psp_v15_0_8_irq_process, }; +static void psp_v15_0_8_ual_cmd_cfg_update(struct amdgpu_psp_irq_mgr *mgr, + u32 event_id, + struct amdgpu_iv_entry *entry) +{ + struct amdgpu_device *adev = mgr->psp->adev; + + amdgpu_ualink_config_update_handler(adev); +} + +static void psp_v15_0_8_ual_cmd_pause(struct amdgpu_psp_irq_mgr *mgr, + u32 event_id, + struct amdgpu_iv_entry *entry) +{ + struct amdgpu_device *adev = mgr->psp->adev; + + amdgpu_ualink_pause_handler(adev); +} + +static void psp_v15_0_8_ual_cmd_resume(struct amdgpu_psp_irq_mgr *mgr, + u32 event_id, + struct amdgpu_iv_entry *entry) +{ + struct amdgpu_device *adev = mgr->psp->adev; + + amdgpu_ualink_resume_handler(adev); +} + +static const struct amdgpu_psp_irq_handler psp_v15_0_8_ual_irq_handlers[] = { + { + .event_id = PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE, + .callback = psp_v15_0_8_ual_cmd_cfg_update, + }, + { + .event_id = PSP_GFX_INT_CTXT_UAL_CMD_PAUSE, + .callback = psp_v15_0_8_ual_cmd_pause, + }, + { + .event_id = PSP_GFX_INT_CTXT_UAL_CMD_RESUME, + .callback = psp_v15_0_8_ual_cmd_resume, + }, +}; + static int psp_v15_0_8_register_irq_handler(struct amdgpu_psp_irq_mgr *mgr, struct amdgpu_irq_src *irq_src) { @@ -443,7 +485,11 @@ static int psp_v15_0_8_register_irq_handler(struct amdgpu_psp_irq_mgr *mgr, if (ret) return ret; - return 0; + ret = amdgpu_psp_irq_mgr_register( + mgr, psp_v15_0_8_ual_irq_handlers, + ARRAY_SIZE(psp_v15_0_8_ual_irq_handlers), NULL); + + return ret; } static const struct psp_funcs psp_v15_0_8_funcs = { -- 2.55.0
