Remove obsolete ras mp1 v13 manager code.
Signed-off-by: YiPeng Chai <[email protected]>
---
drivers/gpu/drm/amd/ras/core/ras.h | 9 -
drivers/gpu/drm/amd/ras/ras_mgr/Makefile | 1 -
.../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 1 -
.../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c | 161 ------------------
.../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h | 30 ----
5 files changed, 202 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
delete mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h
diff --git a/drivers/gpu/drm/amd/ras/core/ras.h
b/drivers/gpu/drm/amd/ras/core/ras.h
index 47fa30f94a2a..73e3960c7c8e 100644
--- a/drivers/gpu/drm/amd/ras/core/ras.h
+++ b/drivers/gpu/drm/amd/ras/core/ras.h
@@ -205,15 +205,6 @@ struct ras_psp;
struct ras_eeprom_mgr;
struct ras_mp1_sys_func {
- int (*mp1_get_valid_bank_count)(struct ras_core_context *ras_core,
- u32 msg, u32 *count);
- int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
- u32 msg, u32 idx, u32 reg_idx, u64 *val);
- int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
- u32 msg_id, uint32_t param, uint32_t *read_arg);
- int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
- uint64_t *enabled_mask);
- int (*mp1_set_debug_mode)(struct ras_core_context *ras_core, bool
enable);
int (*mp1_send_ras_msg)(struct ras_core_context *ras_core, u32 msg_id,
u32 *params, u32 num_params, u32 *read_args, u32 num_read_args);
int (*check_ras_feature_status)(struct ras_core_context *ras_core,
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile
b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile
index 4f94c97c15ca..c70760f10ffd 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile
@@ -21,7 +21,6 @@
RAS_MGR_FILES = amdgpu_ras_sys.o \
amdgpu_ras_mgr.o \
amdgpu_ras_eeprom_i2c.o \
- amdgpu_ras_mp1_v13_0.o \
amdgpu_ras_mp1.o \
amdgpu_ras_cmd.o \
amdgpu_virt_ras_cmd.o \
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
index 7dd8a331bd1d..07dd62ae460b 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
@@ -30,7 +30,6 @@
#include "amdgpu_virt_ras_cmd.h"
#include "amdgpu_ras_process.h"
#include "amdgpu_ras_eeprom_i2c.h"
-#include "amdgpu_ras_mp1_v13_0.h"
#include "amdgpu_ras_mp1.h"
#include "amdgpu_ras_nbio_v7_9.h"
#include "amdgpu_ras_bert.h"
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
deleted file mode 100644
index 548594373d0b..000000000000
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
- * Copyright 2025 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "amdgpu_smu.h"
-#include "amdgpu_reset.h"
-#include "amdgpu_ras_mp1_v13_0.h"
-#include "smu13_driver_if_v13_0_6.h"
-
-#define RAS_MP1_MSG_QueryValidMcaCeCount 0x3A
-#define RAS_MP1_MSG_McaBankCeDumpDW 0x3B
-
-static const enum smu_message_type pmfw_eeprom_msgs[] = {
- [RAS_SMU_GetRASTableVersion] = SMU_MSG_GetRASTableVersion,
- [RAS_SMU_GetBadPageCount] = SMU_MSG_GetBadPageCount,
- [RAS_SMU_SetTimestamp] = SMU_MSG_SetTimestamp,
- [RAS_SMU_GetTimestamp] = SMU_MSG_GetTimestamp,
- [RAS_SMU_GetBadPageIpid] = SMU_MSG_GetBadPageIpid,
- [RAS_SMU_EraseRasTable] = SMU_MSG_EraseRasTable,
- [RAS_SMU_GetBadPageMcaAddr] = SMU_MSG_GetBadPageMcaAddr,
-};
-
-static int mp1_v13_send_smu_msg(struct amdgpu_device *adev, enum
smu_message_type msg,
- uint32_t param, uint32_t *read_arg)
-{
- return amdgpu_smu_ras_send_msg(adev, msg, ¶m, 1, read_arg, read_arg
? 1 : 0);
-}
-
-static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core,
- u32 msg, u32 *count)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
- u32 smu_msg;
- int ret = 0;
-
- if (!count)
- return -EINVAL;
-
- smu_msg = (msg == RAS_MP1_MSG_QueryValidMcaCeCount) ?
- SMU_MSG_QueryValidMcaCeCount :
SMU_MSG_QueryValidMcaCount;
-
- if (down_read_trylock(&adev->reset_domain->sem)) {
- ret = mp1_v13_send_smu_msg(adev, smu_msg, 0, count);
- up_read(&adev->reset_domain->sem);
- } else {
- ret = -RAS_CORE_GPU_IN_MODE1_RESET;
- }
-
- if (ret)
- *count = 0;
-
- return ret;
-}
-
-static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core,
- u32 msg, u32 idx, u32 reg_idx, u64 *val)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
- uint32_t data[2] = {0, 0};
- uint32_t param;
- int ret = 0;
- int i, offset;
- u32 smu_msg = (msg == RAS_MP1_MSG_McaBankCeDumpDW) ?
- SMU_MSG_McaBankCeDumpDW : SMU_MSG_McaBankDumpDW;
-
- if (down_read_trylock(&adev->reset_domain->sem)) {
- offset = reg_idx * 8;
- for (i = 0; i < ARRAY_SIZE(data); i++) {
- param = ((idx & 0xffff) << 16) | ((offset + (i << 2)) &
0xfffc);
- ret = mp1_v13_send_smu_msg(adev, smu_msg, param,
&data[i]);
- if (ret) {
- RAS_DEV_ERR(adev, "ACA failed to read
register[%d], offset:0x%x\n",
- reg_idx, offset);
- break;
- }
- }
- up_read(&adev->reset_domain->sem);
-
- if (!ret)
- *val = (uint64_t)data[1] << 32 | data[0];
- } else {
- ret = -RAS_CORE_GPU_IN_MODE1_RESET;
- }
-
- return ret;
-}
-
-static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
- u32 msg_id, uint32_t param, uint32_t *read_arg)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
- int ret = 0;
-
- if (down_read_trylock(&adev->reset_domain->sem)) {
- ret = mp1_v13_send_smu_msg(adev,
- pmfw_eeprom_msgs[msg_id], param, read_arg);
- up_read(&adev->reset_domain->sem);
- } else {
- ret = -RAS_CORE_GPU_IN_MODE1_RESET;
- }
-
- return ret;
-}
-
-static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
- uint64_t *enabled_mask)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
- int ret = 0;
-
- if (down_read_trylock(&adev->reset_domain->sem)) {
- if (amdgpu_smu_ras_feature_is_enabled(adev,
SMU_FEATURE_HROM_EN_BIT))
- *enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
- up_read(&adev->reset_domain->sem);
- } else {
- ret = -RAS_CORE_GPU_IN_MODE1_RESET;
- }
-
- return ret;
-}
-
-static int mp1_v13_0_set_debug_mode(struct ras_core_context *ras_core, bool
enable)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
- u32 param = enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK |
- ClearMcaOnRead_CE_POLL_MASK;
- int ret;
- u32 smu_msg = SMU_MSG_ClearMcaOnRead;
-
- ret = amdgpu_smu_ras_send_msg(adev, smu_msg,
- ¶m, 1, NULL, 0);
- return ret;
-}
-
-const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
- .mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
- .mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
- .mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
- .mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
- .mp1_set_debug_mode = mp1_v13_0_set_debug_mode,
-};
-
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h
b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h
deleted file mode 100644
index 71c614ae1ae4..000000000000
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright 2025 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __AMDGPU_RAS_MP1_V13_0_H__
-#define __AMDGPU_RAS_MP1_V13_0_H__
-#include "ras.h"
-
-extern const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0;
-
-#endif
--
2.43.0
