On Tuesday 10/27 at 13:35 -0700, Calvin Owens wrote:
> After commit a637a140ab860310 ("drm/amd/display: Allocate DCN32/1 dmub
> memory to GTT"), a machine with a Radeon RX 7900 shows random garbage on
> the screen. It reproduces sporadically, but at times it is so bad the
> machine is more or less unusable.
>
> The garbage is always horizontal bars extending across the entire
> screen, always approximately 200 pixels tall on a 3840x2160 screen,
> for what looks like a single frame. The bars are mostly black, but will
> sometimes exhibit striping and periodic artifacts which smell like
> non-framebuffer data is being rendered to the screen.
>
> It took some patience on the "good" side, but I was able to nail it down
> to commit a637a140ab860310818a14fb4d37e39e51a06be4 with this bisect:
>
> bad: [cee9395acd8043be0644b25c34bfa86623f2b935] Linux 7.3-rc1
> good: [8d3ae59288f1e7d58d76558a6ee96d533bc5019f] Linux 7.2
> good: [55ab7e14222e5f0b0fd9f7711ca391d2924b35e3] Merge tag
> 'for-7.3/block-20260819' of
> git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux
> bad: [df51bdc5e80dae43cab81f6cc641e98638303c88] Merge tag 'mtd/for-7.3' of
> git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
> bad: [29daacacf4cd84e6917f09de6a99fb170071c14c] Merge tag
> 'drm-rust-next-2026-08-08' of https://gitlab.freedesktop.org/drm/rust/kernel
> into drm-next
> good: [fff648aec5e2790d117a0ec5c849a284d9d33d70] drm/amdgpu: include
> amdgpu_video_codecs.h only where needed
> bad: [336e0cd576817ac64a4b394ca2b3680029f3e37f] Revert "drm/amdgpu: fix
> aperture mapping leak"
> bad: [789f7486a384ca58b9d7a76abba5efa0e80e8dab] drm/amd/display: Test plane
> colorop helper walkers
> good: [e0e426f10ad653c5e9dd33fb4a76d55f06101992] drm/amd/display: Test
> helper_check_state rejects
> bad: [982b2a43682b55e7d9800000f2592832ff2865ba] drm/amdgpu: Fix IP block
> NULL check during soft reset
> bad: [9102b39fa924dcc3dc75a3137bfa9633c40b88c0] drm/amdgpu/userq: fix
> indefinite fence wait during GPU reset
> bad: [b23470a026afe64de5c1df4ad181587b49c22923] drm/amd/display: Exit LS
> for ISHARP before coefficient write
> bad: [f02b2e47355e9d381a7f34acc997e1c47879ca21] drm/amd/display: Add KUnit
> test for wb jobs
> bad: [c6a13d145cc811b19c8a0620f25868cf7d5700c0] drm/amd/display: remove
> unused dcn42 socbb values
> good: [1d8327353de6f1f34063840f362c208c84064f54] drm/amd/display: Fix VABC
> Init and OLED Support
> bad: [a637a140ab860310818a14fb4d37e39e51a06be4] drm/amd/display: Allocate
> DCN32/1 dmub memory to GTT
> first 'bad' commit: [a637a140ab860310818a14fb4d37e39e51a06be4]
> drm/amd/display: Allocate DCN32/1 dmub memory to GTT
>
> Sure enough, reverting a637a140ab860310818a14fb4d37e39e51a06be4 on top
> of v7.3 completely and totally eliminates the problem for me.
>
> Mikhail has separately reported this regression:
>
>
> https://lore.kernel.org/all/[email protected]/
>
> ...but it seems to be much more consistent for me than for Mikhail, it's
> never taken more than 30 minutes even when the machine is completely
> idle. I've also never been able to reproduce any artifact one single
> time without commit a637a140, despite a lot of effort.
>
> I'm not sure reverting this is the right way forward, since presumably
> this would re-regress the timing issue Fangzhi alluded to in the
> original commit. But nobody has proposed anything concrete yet... so
> let's start the discussion here.
>
> I'm happy to help test other better ideas as well :)
Friendly ping.
> Signed-off-by: Calvin Owens <[email protected]>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 11 ++---------
> 1 file changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
> index 9ff25bc8ee5ae..870534b7cf46d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
> @@ -511,7 +511,6 @@ int dm_dmub_sw_init(struct amdgpu_device *adev)
> DMUB_WINDOW_MEMORY_TYPE_FB, /*
> DMUB_WINDOW_CURSOR_OFFLOAD */
> };
> int r;
> - int mem_domain = AMDGPU_GEM_DOMAIN_GTT;
>
> switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
> case IP_VERSION(2, 1, 0):
> @@ -648,19 +647,13 @@ int dm_dmub_sw_init(struct amdgpu_device *adev)
> return -EINVAL;
> }
>
> - /* Limit to allocate dmub to GTT on DCN32/1
> - * TODO: Other asics with GDDR7 may have worse latency
> - */
> - if (dmub_asic != DMUB_ASIC_DCN32 &&
> - dmub_asic != DMUB_ASIC_DCN321)
> - mem_domain |= AMDGPU_GEM_DOMAIN_VRAM;
> -
> /*
> * Allocate a framebuffer based on the total size of all the regions.
> * TODO: Move this into GART.
> */
> r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
> - mem_domain,
> + AMDGPU_GEM_DOMAIN_VRAM |
> + AMDGPU_GEM_DOMAIN_GTT,
> &adev->dm.dmub_bo,
> &adev->dm.dmub_bo_gpu_addr,
> &adev->dm.dmub_bo_cpu_addr);
> --
> 2.47.3
>
