This reverts commit 521bedfc94cc. The patch sets AMDGPU_PTE_SYSTEM in amdgpu_ttm_tt_pde_flags() and converts the VRAM address with amdgpu_gmc_vram_mc2pa() inside amdgpu_gmc_get_pde_for_bo(). gmc_v12_1_get_vm_pde() already converts an MC address to a physical address and skips that conversion when the SYSTEM bit is set, so setting the bit first bypasses the translation.
The bit belongs in the GFX 12.1 helpers, after that translation. PDB0 is written directly and does not go through get_vm_pde(), and NPA still requires PTE.S=0, so those two pieces come back in the following patch. Signed-off-by: Zhigang Luo <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 +++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 1 - 4 files changed, 3 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 4204c3c750a8..659e89e5e78f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -122,11 +122,6 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, break; case TTM_PL_VRAM: *addr = amdgpu_bo_gpu_offset(bo); - /* For SPM-backed VRAM, convert the MC address to a physical - * address for system memory path access. - */ - if (amdgpu_virt_vram_is_spm(adev)) - *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); break; default: *addr = 0; @@ -1286,8 +1281,6 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; flags |= AMDGPU_PTE_WRITEABLE; flags |= AMDGPU_PTE_SNOOPED; - if (amdgpu_virt_vram_is_spm(adev)) - flags |= AMDGPU_PTE_SYSTEM; flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); flags |= AMDGPU_PDE_PTE_FLAG(adev); @@ -1307,8 +1300,6 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) * pointing to a 4K system page */ flags = AMDGPU_PTE_VALID; - if (amdgpu_virt_vram_is_spm(adev)) - flags |= AMDGPU_PTE_SYSTEM; flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PDE_BFS_FLAG(adev, 0); /* Requires gart_ptb_gpu_pa to be 4K aligned */ amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 212d86adffd8..37f7f421b470 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1461,17 +1461,9 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) flags |= AMDGPU_PTE_SNOOPED; } - if (mem && mem->mem_type == TTM_PL_VRAM) { - if (mem->bo) { - struct amdgpu_device *adev = amdgpu_ttm_adev(mem->bo->bdev); - - if (amdgpu_virt_vram_is_spm(adev)) - flags |= AMDGPU_PTE_SYSTEM; - } - - if (mem->bus.caching == ttm_cached) - flags |= AMDGPU_PTE_SNOOPED; - } + if (mem && mem->mem_type == TTM_PL_VRAM && + mem->bus.caching == ttm_cached) + flags |= AMDGPU_PTE_SNOOPED; return flags; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c index 11f022c56667..3bb426b33af9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c @@ -6171,7 +6171,6 @@ static int amdgpu_ualink_peer_remote_init(struct amdgpu_device *adev) flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, bo->tbo.resource); flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT_GFX12 | AMDGPU_PTE_BUS_ATOMICS; flags &= ~AMDGPU_PTE_VALID; - flags &= ~AMDGPU_PTE_SYSTEM; /* PTE.X=0 turn off RPC checks for RBs, wptr and doorbell NPA address */ flags &= ~AMDGPU_PTE_EXECUTABLE; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index b67683012002..76391fca6c62 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -616,7 +616,6 @@ static void gmc_v12_1_get_npa_flags(struct amdgpu_device *adev, *flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT_GFX12 | AMDGPU_PTE_BUS_ATOMICS; *flags &= ~AMDGPU_PTE_VALID; - *flags &= ~AMDGPU_PTE_SYSTEM; *flags &= ~AMDGPU_PTE_EXECUTABLE; } -- 2.43.0
