Re: [PATCH] drm/amdgpu: Add CLK IP base offset

[Quan, Evan]

Reviewed-by: Evan Quan <evan.q...@amd.com>

________________________________
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of Rex Zhu 
<rex....@amd.com>
Sent: Thursday, July 5, 2018 4:39:44 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amdgpu: Add CLK IP base offset

so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Signed-off-by: Rex Zhu <rex....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h          | 1 +
 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 44bcc3e..8eaba0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1401,6 +1401,7 @@ enum amd_hw_ip_block_type {
         PWR_HWIP,
         NBIF_HWIP,
         THM_HWIP,
+       CLK_HWIP,
         MAX_HWIP
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 45aafca..c5c9b2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -51,6 +51,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
                 adev->reg_offset[PWR_HWIP][i] = (uint32_t 
*)(&(PWR_BASE.instance[i]));
                 adev->reg_offset[NBIF_HWIP][i] = (uint32_t 
*)(&(NBIF_BASE.instance[i]));
                 adev->reg_offset[THM_HWIP][i] = (uint32_t 
*)(&(THM_BASE.instance[i]));
+               adev->reg_offset[CLK_HWIP][i] = (uint32_t 
*)(&(CLK_BASE.instance[i]));
         }
         return 0;
 }
--
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx