The other one i after driver enable the CP interrupt (set register CP_INT_CNTL_RING0) . I think it still needed but maybe can be moved under if statement
Regards shaoyun.liu On 2018-11-22 12:18 p.m., Kuehling, Felix wrote: > On 2018-11-22 12:03 p.m., Liu, Shaoyun wrote: >> Driver shouldn't try to access any GFX registers until RLC is idle. >> During the test, it took 12 seconds for RLC to clear the BUSY bit >> in RLC_GPM_STAT register which is un-acceptable for driver. >> As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK >> cycles to finish its critical section. In a lowest 300M enginer clock >> setting(default from vbios), 50 us delay is enough. >> >> Change-Id: If074fbeeecad3f63cf5f5ab232472d0fe46082a6 >> Signed-off-by: shaoyunl <shaoyun....@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> index e409fbf..2e3ee42 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> @@ -2326,6 +2326,7 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device >> *adev) >> #endif >> >> WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); >> + udelay(50); >> >> /* carrizo do enable cp interrupt after cp inited */ >> if (!(adev->flags & AMD_IS_APU)) > gfx_v9_0_enable_gui_idle_interrupt(adev, true); > > udelay(50); > > There is already another udelay(50) here. Is that one still needed? > > Regards, > Felix > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
