I'm not familiar enough with ARM to know if write combining
is actually an architectural limitation or if it's an issue
with the PCIe IPs used on various platforms, but so far
everyone that has tried to run radeon hardware on
ARM has had to disable it. So let's just make it official.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
include/drm/drm_cache.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index bfe1639df02d..691b4c4b0587 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -47,6 +47,8 @@ static inline bool drm_arch_can_wc_memory(void)
return false;
#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
return false;
+#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+ return false;
#else
return true;
#endif
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
