[PATCH libdrm] amdgpu: update amdgpu_drm.h

[Marek Olšák]

From: Marek Olšák <marek.ol...@amd.com>

---
 include/drm/amdgpu_drm.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 1ceec56d..be84e43c 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -319,20 +319,26 @@ struct drm_amdgpu_gem_userptr {
 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT                        17
 #define AMDGPU_TILING_BANK_HEIGHT_MASK                 0x3
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT          19
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK           0x3
 #define AMDGPU_TILING_NUM_BANKS_SHIFT                  21
 #define AMDGPU_TILING_NUM_BANKS_MASK                   0x3
 
 /* GFX9 and later: */
 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT               0
 #define AMDGPU_TILING_SWIZZLE_MODE_MASK                        0x1f
+#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT            5
+#define AMDGPU_TILING_DCC_OFFSET_256B_MASK             0xFFFFFF
+#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT              29
+#define AMDGPU_TILING_DCC_PITCH_MAX_MASK               0x3FFF
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT                43
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK         0x1
 
 /* Set/Get helpers for tiling flags. */
 #define AMDGPU_TILING_SET(field, value) \
        (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << 
AMDGPU_TILING_##field##_SHIFT)
 #define AMDGPU_TILING_GET(value, field) \
        (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & 
AMDGPU_TILING_##field##_MASK)
 
 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 
@@ -658,20 +664,22 @@ struct drm_amdgpu_cs_chunk_data {
        /* Subquery id: Query PSP ASD firmware version */
        #define AMDGPU_INFO_FW_ASD              0x0d
        /* Subquery id: Query VCN firmware version */
        #define AMDGPU_INFO_FW_VCN              0x0e
        /* Subquery id: Query GFX RLC SRLC firmware version */
        #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
        /* Subquery id: Query GFX RLC SRLG firmware version */
        #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
        /* Subquery id: Query GFX RLC SRLS firmware version */
        #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
+       /* Subquery id: Query DMCU firmware version */
+       #define AMDGPU_INFO_FW_DMCU             0x12
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED            0x0f
 /* the used VRAM size */
 #define AMDGPU_INFO_VRAM_USAGE                 0x10
 /* the used GTT size */
 #define AMDGPU_INFO_GTT_USAGE                  0x11
 /* Information about GDS, etc. resource configuration */
 #define AMDGPU_INFO_GDS_CONFIG                 0x13
 /* Query information about VRAM and GTT domains */
 #define AMDGPU_INFO_VRAM_GTT                   0x14
-- 
2.17.1

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