From: Hawking Zhang <[email protected]>

The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits

Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 9 +++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +++++-
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 4f10f5aba00b..568c0f61b4d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1574,8 +1574,13 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
        flags &= ~AMDGPU_PTE_EXECUTABLE;
        flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 
-       flags &= ~AMDGPU_PTE_MTYPE_MASK;
-       flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
+       if (adev->asic_type == CHIP_NAVI10) {
+               flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
+               flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
+       } else {
+               flags &= ~AMDGPU_PTE_MTYPE_MASK;
+               flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
+       }
 
        if ((mapping->flags & AMDGPU_PTE_PRT) &&
            (adev->asic_type >= CHIP_VEGA10)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 91baf95212a6..c4125b477138 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -75,7 +75,7 @@ struct amdgpu_bo_list_entry;
 
 
 /* For GFX9 */
-#define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)
+#define AMDGPU_PTE_MTYPE(a)    ((uint64_t)(a) << 57)
 #define AMDGPU_PTE_MTYPE_MASK  AMDGPU_PTE_MTYPE(3ULL)
 
 #define AMDGPU_MTYPE_NC 0
@@ -88,6 +88,10 @@ struct amdgpu_bo_list_entry;
                                 | AMDGPU_PTE_WRITEABLE  \
                                 | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
 
+/* NAVI10 only */
+#define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
+#define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)
+
 /* How to programm VM fault handling */
 #define AMDGPU_VM_FAULT_STOP_NEVER     0
 #define AMDGPU_VM_FAULT_STOP_FIRST     1
-- 
2.20.1

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