[PATCH 3/6] drm/amdgpu: initialize new parameters and functions for amdgpu_umc structure

[Tao Zhou]

Signed-off-by: Tao Zhou <tao.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  7 +++++--
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++++++-
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h |  3 +++
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ee06cbe2a7e7..3486b4ce7770 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -631,8 +631,11 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device 
*adev)
 {
        switch (adev->asic_type) {
        case CHIP_VEGA20:
-               adev->umc.max_ras_err_cnt_per_query =
-                       UMC_V6_1_UMC_INSTANCE_NUM * 
UMC_V6_1_CHANNEL_INSTANCE_NUM;
+               adev->umc.max_ras_err_cnt_per_query = 
UMC_V6_1_TOTAL_CHANNEL_NUM;
+               adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
+               adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
+               adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;
+               adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
                adev->umc.funcs = &umc_v6_1_funcs;
                break;
        default:
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 035e4fea472c..9ba015d7eb57 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -41,7 +41,7 @@
 /* offset in 256B block */
 #define OFFSET_IN_256B_BLOCK(addr)             ((addr) & 0xffULL)
 
-static uint32_t
+const uint32_t
        
umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM]
 = {
                {2, 18, 11, 27},        {4, 20, 13, 29},
                {1, 17, 8, 24},         {7, 23, 14, 30},
@@ -235,7 +235,15 @@ static void umc_v6_1_query_ras_error_address(struct 
amdgpu_device *adev,
        umc_v6_1_disable_umc_index_mode(adev);
 }
 
+static void umc_v6_1_ras_init(struct amdgpu_device *adev)
+{
+
+}
+
 const struct amdgpu_umc_funcs umc_v6_1_funcs = {
+       .ras_init = umc_v6_1_ras_init,
        .query_ras_error_count = umc_v6_1_query_ras_error_count,
        .query_ras_error_address = umc_v6_1_query_ras_error_address,
+       .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
+       .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
index bddaf14a77f9..ad4598c0e495 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
@@ -24,6 +24,7 @@
 #define __UMC_V6_1_H__
 
 #include "soc15_common.h"
+#include "amdgpu.h"
 
 /* HBM  Memory Channel Width */
 #define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH      128
@@ -37,5 +38,7 @@
 #define UMC_V6_1_PER_CHANNEL_OFFSET            0x800
 
 extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
+extern const uint32_t
+       
umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
 
 #endif
-- 
2.17.1

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