Reviewed-by: Xiaojie Yuan <xiaojie.y...@amd.com>
BR,
Xiaojie
> On Aug 5, 2019, at 10:20 AM, Xu, Feifei <feifei...@amd.com> wrote:
>
> Reviewed-by: Feifei Xu <feifei...@amd.com>
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Gao Likun
> Sent: Monday, August 5, 2019 10:07 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <alexander.deuc...@amd.com>; Gao, Likun
> <likun....@amd.com>; Paul Gover <pmw.go...@yahoo.co.uk>; Yuan, Xiaojie
> <xiaojie.y...@amd.com>
> Subject: [PATCH] drm/amdgpu: pin the csb buffer on hw init for gfx v8
>
> From: Likun Gao <likun....@amd.com>
>
> Without this pin, the csb buffer will be filled with inconsistent data after
> S3 resume. And that will causes gfx hang on gfxoff exit since this csb will
> be executed then.
>
> Signed-off-by: Likun Gao <likun....@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index d290718..98e5aa8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1317,6 +1317,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device
> *adev)
> return 0;
> }
>
> +static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev) {
> + int r;
> +
> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> + if (unlikely(r != 0))
> + return r;
> +
> + r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> + AMDGPU_GEM_DOMAIN_VRAM);
> + if (!r)
> + adev->gfx.rlc.clear_state_gpu_addr =
> + amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
> +
> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> +
> + return r;
> +}
> +
> +static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev) {
> + int r;
> +
> + if (!adev->gfx.rlc.clear_state_obj)
> + return;
> +
> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> + if (likely(r == 0)) {
> + amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> + }
> +}
> +
> static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) {
> amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); @@ -4791,6
> +4824,10 @@ static int gfx_v8_0_hw_init(void *handle)
> gfx_v8_0_init_golden_registers(adev);
> gfx_v8_0_constants_init(adev);
>
> + r = gfx_v8_0_csb_vram_pin(adev);
> + if (r)
> + return r;
> +
> r = adev->gfx.rlc.funcs->resume(adev);
> if (r)
> return r;
> @@ -4907,6 +4944,9 @@ static int gfx_v8_0_hw_fini(void *handle)
> else
> pr_err("rlc is busy, skip halt rlc\n");
> amdgpu_gfx_rlc_exit_safe_mode(adev);
> +
> + gfx_v8_0_csb_vram_unpin(adev);
> +
> return 0;
> }
>
> --
> 2.7.4
>
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