[PATCH 36/39] drm/amd/display: Formula refactor for calculating DPP CLK DTO

[Rodrigo Siqueira]

From: Sung Lee <sung....@amd.com>

[Why]
Previous formula for calculating DPP CLK DTO was
hard to understand.

[How]
Replace with easier to understand formula that produces
same results.

Signed-off-by: Sung Lee <sung....@amd.com>
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 20 +++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index 1e1151356e60..50bffbfdd394 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -50,20 +50,20 @@ void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, 
int req_dppclk)
 
        if (dccg->ref_dppclk && req_dppclk) {
                int ref_dppclk = dccg->ref_dppclk;
+               int modulo, phase;
 
-               ASSERT(req_dppclk <= ref_dppclk);
-               /* need to clamp to 8 bits */
-               if (ref_dppclk > 0xff) {
-                       int divider = (ref_dppclk + 0xfe) / 0xff;
+               // phase / modulo = dpp pipe clk / dpp global clk
+               modulo = 0xff;   // use FF at the end
+               phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
 
-                       ref_dppclk /= divider;
-                       req_dppclk = (req_dppclk + divider - 1) / divider;
-                       if (req_dppclk > ref_dppclk)
-                               req_dppclk = ref_dppclk;
+               if (phase > 0xff) {
+                       ASSERT(false);
+                       phase = 0xff;
                }
+
                REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
-                               DPPCLK0_DTO_PHASE, req_dppclk,
-                               DPPCLK0_DTO_MODULO, ref_dppclk);
+                               DPPCLK0_DTO_PHASE, phase,
+                               DPPCLK0_DTO_MODULO, modulo);
                REG_UPDATE(DPPCLK_DTO_CTRL,
                                DPPCLK_DTO_ENABLE[dpp_inst], 1);
        } else {
-- 
2.24.0

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