[AMD Official Use Only - Internal Distribution Only]
>-----Original Message-----
>From: Zhang, Jack (Jian) <jack.zha...@amd.com>
>Sent: Friday, December 27, 2019 3:00 PM
>To: Feng, Kenneth <kenneth.f...@amd.com>; Deucher, Alexander
><alexander.deuc...@amd.com>; Quan, Evan <evan.q...@amd.com>; Wang,
>Kevin(Yang) <kevin1.w...@amd.com>; Tao, Yintian <yintian....@amd.com>;
>Deng, Emily <emily.d...@amd.com>; Min, Frank <frank....@amd.com>; Liu,
>Monk <monk....@amd.com>; amd-gfx@lists.freedesktop.org; Zhang, Jack (Jian)
><jack.zha...@amd.com>
>Subject: RE: [PATCH 1/2] amd/amdgpu/sriov enable onevf mode for ARCTURUS
>VF
>
>
>
>-----Original Message-----
>From: Jack Zhang <jack.zha...@amd.com>
>Sent: Friday, December 27, 2019 2:57 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhang, Jack (Jian) <jack.zha...@amd.com>
>Subject: [PATCH 1/2] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF
>
>Before, initialization of smu ip block would be skipped for sriov ASICs. But if
>there's only one VF being used, guest driver should be able to dump some HW
>info such as clks, temperature,etc.
>
>To solve this, now after onevf mode is enabled, host driver will notify guest.
>If
>it's onevf mode, guest will do smu hw_init and skip some steps in normal smu
>hw_init flow because host driver has already done it for smu.
>
>With this fix, guest app can talk with smu and dump hw information from smu.
>
>v2: refine the logic for pm_enabled.Skip hw_init by not changing pm_enabled.
>
>Signed-off-by: Jack Zhang <jack.zha...@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +-
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 45 +++++++++++++++++------
>-------
> 3 files changed, 29 insertions(+), 22 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>index 8469834..08130a6 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>@@ -1448,7 +1448,8 @@ static int psp_np_fw_load(struct psp_context *psp)
> || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
> || ucode->ucode_id ==
>AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
> || ucode->ucode_id ==
>AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
>- || ucode->ucode_id ==
>AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM))
>+ || ucode->ucode_id ==
>AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
>+ || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
> /*skip ucode loading in SRIOV VF */
> continue;
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>b/drivers/gpu/drm/amd/amdgpu/soc15.c
>index b53d401..a271496 100644
>--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>@@ -827,8 +827,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev,
>&dce_virtual_ip_block);
> amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
> amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
>- if (!amdgpu_sriov_vf(adev))
>- amdgpu_device_ip_block_add(adev,
>&smu_v11_0_ip_block);
>+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
>
> if (amdgpu_sriov_vf(adev)) {
> if (likely(adev->firmware.load_type ==
>AMDGPU_FW_LOAD_PSP)) diff --git
>a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
>b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
>index 936c682..42c0a6d 100644
>--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
>+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
>@@ -531,10 +531,14 @@ bool is_support_sw_smu(struct amdgpu_device
>*adev)
> if (adev->asic_type == CHIP_VEGA20)
> return (amdgpu_dpm == 2) ? true : false;
> else if (adev->asic_type >= CHIP_ARCTURUS) {
>- if (amdgpu_sriov_vf(adev))
>- return false;
>- else
>+ if (amdgpu_sriov_vf(adev)) {
>+ if(amdgpu_sriov_is_pp_one_vf(adev))
>+ return true;
>+ else
>+ return false;
>+ } else {
> return true;
>+ }
> } else
> return false;
> }
>@@ -1062,20 +1066,19 @@ static int smu_smc_table_hw_init(struct
>smu_context *smu,
> }
>
> /* smu_dump_pptable(smu); */
>+ if(amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)){
>+ /*
>+ * Copy pptable bo in the vram to smc with SMU MSGs such as
>+ * SetDriverDramAddr and TransferTableDram2Smu.
>+ */
>+ ret = smu_write_pptable(smu);
>+ if (ret)
>+ return ret;
Why only sriov and non one vf mode need to this? What about bare metal?
>
>- /*
>- * Copy pptable bo in the vram to smc with SMU MSGs such as
>- * SetDriverDramAddr and TransferTableDram2Smu.
>- */
>- ret = smu_write_pptable(smu);
>- if (ret)
>- return ret;
>-
>- /* issue Run*Btc msg */
>- ret = smu_run_btc(smu);
>- if (ret)
>- return ret;
>-
>+ /* issue Run*Btc msg */
>+ ret = smu_run_btc(smu);
>+ if (ret)
>+ return ret;
> ret = smu_feature_set_allowed_mask(smu);
> if (ret)
> return ret;
>@@ -1083,7 +1086,7 @@ static int smu_smc_table_hw_init(struct
>smu_context *smu,
> ret = smu_system_features_control(smu, true);
> if (ret)
> return ret;
>-
>+ }
> if (adev->asic_type != CHIP_ARCTURUS) {
> ret = smu_notify_display_change(smu);
> if (ret)
>@@ -1136,8 +1139,9 @@ static int smu_smc_table_hw_init(struct
>smu_context *smu,
> /*
> * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for
>tools.
> */
>- ret = smu_set_tool_table_location(smu);
>-
>+ if(amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)){
>+ ret = smu_set_tool_table_location(smu);
>+ }
> if (!smu_is_dpm_running(smu))
> pr_info("dpm has been disabled\n");
>
>@@ -1249,6 +1253,9 @@ static int smu_hw_init(void *handle)
> smu_set_gfx_cgpg(&adev->smu, true);
> }
>
>+ if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
>+ return 0;
>+
> if (!smu->pm_enabled)
> return 0;
>
>--
>2.7.4
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