[AMD Public Use]
I think we can implement it by only updating amdgpu_umc_for_each_channel macro,
here is an example:
#define amdgpu_umc_for_each_channel(func) \
struct ras_err_data *err_data = \
(struct ras_err_data *)ras_error_status; \
uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \
for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; \
umc_inst++) { \
umc_reg_offset = adev->umc.inst_offs * umc_inst; \
for (channel_inst = 0; \
channel_inst < adev->umc.channel_inst_num; \
channel_inst++) { \
/* get channel index of interleaved memory */ \
channel_index = adev->umc.channel_idx_tbl[\
umc_inst * adev->umc.channel_inst_num +
channel_inst]; \
(func)(adev, err_data, umc_reg_offset, channel_index); \
/* increase register offset for next channel */ \
umc_reg_offset += adev->umc.channel_offs; \
} \
}
Regards,
Tao
From: Clements, John <john.cleme...@amd.com>
Sent: 2020年1月2日 18:31
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking <hawking.zh...@amd.com>;
Zhou1, Tao <tao.zh...@amd.com>
Subject: [PATCH] drm/amdgpu: resolved bug in UMC 6 error counter query
[AMD Official Use Only - Internal Distribution Only]
Added patch to resolve following issue where error counter detection was not
iterating over all UMC instances/channels.
Removed support for accessing UMC error counters via MMIO.
Thank you,
John Clements
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