[PATCH] drm/amd/amdgpu: Add gfxoff debugfs entry

[Tom St Denis]

Write a 32-bit value of zero to disable GFXOFF and write a 32-bit
value of non-zero to enable GFXOFF.

Signed-off-by: Tom St Denis <tom.stde...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 56 +++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 7379910790c9..3bb74056b9d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -842,6 +842,55 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
        return result;
 }
 
+/**
+ * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
+ *
+ * @f: open file handle
+ * @buf: User buffer to write data from
+ * @size: Number of bytes to write
+ * @pos:  Offset to seek to
+ *
+ * Write a 32-bit zero to disable or a 32-bit non-zero to enable
+ */
+static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user 
*buf,
+                                        size_t size, loff_t *pos)
+{
+       struct amdgpu_device *adev = file_inode(f)->i_private;
+       ssize_t result = 0;
+       int r;
+
+       if (size & 0x3 || *pos & 0x3)
+               return -EINVAL;
+
+       r = pm_runtime_get_sync(adev->ddev->dev);
+       if (r < 0)
+               return r;
+
+       while (size) {
+               uint32_t value;
+
+               r = get_user(value, (uint32_t *)buf);
+               if (r) {
+                       pm_runtime_mark_last_busy(adev->ddev->dev);
+                       pm_runtime_put_autosuspend(adev->ddev->dev);
+                       return r;
+               }
+
+               amdgpu_gfx_off_ctrl(adev, value ? true : false);
+
+               result += 4;
+               buf += 4;
+               *pos += 4;
+               size -= 4;
+       }
+
+       pm_runtime_mark_last_busy(adev->ddev->dev);
+       pm_runtime_put_autosuspend(adev->ddev->dev);
+
+       return result;
+}
+
+
 static const struct file_operations amdgpu_debugfs_regs_fops = {
        .owner = THIS_MODULE,
        .read = amdgpu_debugfs_regs_read,
@@ -890,6 +939,11 @@ static const struct file_operations 
amdgpu_debugfs_gpr_fops = {
        .llseek = default_llseek
 };
 
+static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
+       .owner = THIS_MODULE,
+       .write = amdgpu_debugfs_gfxoff_write,
+};
+
 static const struct file_operations *debugfs_regs[] = {
        &amdgpu_debugfs_regs_fops,
        &amdgpu_debugfs_regs_didt_fops,
@@ -899,6 +953,7 @@ static const struct file_operations *debugfs_regs[] = {
        &amdgpu_debugfs_sensors_fops,
        &amdgpu_debugfs_wave_fops,
        &amdgpu_debugfs_gpr_fops,
+       &amdgpu_debugfs_gfxoff_fops,
 };
 
 static const char *debugfs_regs_names[] = {
@@ -910,6 +965,7 @@ static const char *debugfs_regs_names[] = {
        "amdgpu_sensors",
        "amdgpu_wave",
        "amdgpu_gpr",
+       "amdgpu_gfxoff",
 };
 
 /**
-- 
2.24.1

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