The queues represented in queue_bitmap are only CP queues.

Change-Id: I7e6a75de39718d7c4da608166b85b9377d06d1b3
Signed-off-by: Yong Zhao <yong.z...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c           |  4 ++--
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c    | 12 ++++++------
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h    |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c      |  2 +-
 .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c   |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c            |  2 +-
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h      |  2 +-
 7 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 8609287620ea..ebe4b8f88e79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -126,7 +126,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                /* this is going to have a few of the MSBs set that we need to
                 * clear
                 */
-               bitmap_complement(gpu_resources.queue_bitmap,
+               bitmap_complement(gpu_resources.cp_queue_bitmap,
                                  adev->gfx.mec.queue_bitmap,
                                  KGD_MAX_QUEUES);
 
@@ -137,7 +137,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                                * adev->gfx.mec.num_pipe_per_mec
                                * adev->gfx.mec.num_queue_per_pipe;
                for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
-                       clear_bit(i, gpu_resources.queue_bitmap);
+                       clear_bit(i, gpu_resources.cp_queue_bitmap);
 
                amdgpu_doorbell_get_kfd_info(adev,
                                &gpu_resources.doorbell_physical_address,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 7ef9b89f5c70..973581c2b401 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -78,14 +78,14 @@ static bool is_pipe_enabled(struct device_queue_manager 
*dqm, int mec, int pipe)
        /* queue is available for KFD usage if bit is 1 */
        for (i = 0; i <  dqm->dev->shared_resources.num_queue_per_pipe; ++i)
                if (test_bit(pipe_offset + i,
-                             dqm->dev->shared_resources.queue_bitmap))
+                             dqm->dev->shared_resources.cp_queue_bitmap))
                        return true;
        return false;
 }
 
-unsigned int get_queues_num(struct device_queue_manager *dqm)
+unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
 {
-       return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
+       return bitmap_weight(dqm->dev->shared_resources.cp_queue_bitmap,
                                KGD_MAX_QUEUES);
 }
 
@@ -908,7 +908,7 @@ static int initialize_nocpsch(struct device_queue_manager 
*dqm)
 
                for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
                        if (test_bit(pipe_offset + queue,
-                                    dqm->dev->shared_resources.queue_bitmap))
+                                    
dqm->dev->shared_resources.cp_queue_bitmap))
                                dqm->allocated_queues[pipe] |= 1 << queue;
        }
 
@@ -1029,7 +1029,7 @@ static int set_sched_resources(struct 
device_queue_manager *dqm)
                mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
                        / dqm->dev->shared_resources.num_pipe_per_mec;
 
-               if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
+               if (!test_bit(i, dqm->dev->shared_resources.cp_queue_bitmap))
                        continue;
 
                /* only acquire queues from the first MEC */
@@ -1979,7 +1979,7 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
 
                for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
                        if (!test_bit(pipe_offset + queue,
-                                     dqm->dev->shared_resources.queue_bitmap))
+                                     
dqm->dev->shared_resources.cp_queue_bitmap))
                                continue;
 
                        r = dqm->dev->kfd2kgd->hqd_dump(
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index ee3400e92c30..3f0fb0d28c01 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -219,7 +219,7 @@ void device_queue_manager_init_v10_navi10(
                struct device_queue_manager_asic_ops *asic_ops);
 void program_sh_mem_settings(struct device_queue_manager *dqm,
                                        struct qcm_process_device *qpd);
-unsigned int get_queues_num(struct device_queue_manager *dqm);
+unsigned int get_cp_queues_num(struct device_queue_manager *dqm);
 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm);
 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm);
 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 393c218734fd..377bde0e781c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -62,7 +62,7 @@ static void pm_calc_rlib_size(struct packet_manager *pm,
                max_proc_per_quantum = dev->max_proc_per_quantum;
 
        if ((process_count > max_proc_per_quantum) ||
-           compute_queue_count > get_queues_num(pm->dqm)) {
+           compute_queue_count > get_cp_queues_num(pm->dqm)) {
                *over_subscription = true;
                pr_debug("Over subscribed runlist\n");
        }
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 606b1a8aacad..b62ee2e3344a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -266,7 +266,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
                if ((dev->dqm->sched_policy ==
                     KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
                ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||
-               (dev->dqm->active_queue_count >= get_queues_num(dev->dqm)))) {
+               (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) 
{
                        pr_debug("Over-subscription is not allowed when 
amdkfd.sched_policy == 1\n");
                        retval = -EPERM;
                        goto err_create_queue;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 43a82cf76628..b70e6b25edc6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1318,7 +1318,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
        dev->node_props.num_gws = (dev->gpu->gws &&
                dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
                amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0;
-       dev->node_props.num_cp_queues = get_queues_num(dev->gpu->dqm);
+       dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);
 
        kfd_fill_mem_clk_max_info(dev);
        kfd_fill_iolink_non_crat_info(dev);
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h 
b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index a607b1034962..55750890b73f 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -123,7 +123,7 @@ struct kgd2kfd_shared_resources {
        uint32_t num_queue_per_pipe;
 
        /* Bit n == 1 means Queue n is available for KFD */
-       DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
+       DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
 
        /* SDMA doorbell assignments (SOC15 and later chips only). Only
         * specific doorbells are routed to each SDMA engine. Others
-- 
2.17.1

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