On 2020-03-03 7:50 a.m., Nirmoy Das wrote: > amdgpu statically set priority for compute queues > at initialization so remove all the functions > responsible changing compute queue priority dynamically
If this is just a blob of words and not a proper sentence or paragraph, how can we trust the changes of this patch series? "amdgpu" is "AMDGPU", "sets", end with a period. Regards, Luben > > Signed-off-by: Nirmoy Das <nirmoy....@amd.com> > Reviewed-by: Christian König <christian.koe...@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 70 ---------------- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 7 -- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 99 ---------------------- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 100 ----------------------- > 4 files changed, 276 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > index ca6b52054b4b..a7e1d0425ed0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > @@ -150,76 +150,6 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) > ring->funcs->end_use(ring); > } > > -/** > - * amdgpu_ring_priority_put - restore a ring's priority > - * > - * @ring: amdgpu_ring structure holding the information > - * @priority: target priority > - * > - * Release a request for executing at @priority > - */ > -void amdgpu_ring_priority_put(struct amdgpu_ring *ring, > - enum drm_sched_priority priority) > -{ > - int i; > - > - if (!ring->funcs->set_priority) > - return; > - > - if (atomic_dec_return(&ring->num_jobs[priority]) > 0) > - return; > - > - /* no need to restore if the job is already at the lowest priority */ > - if (priority == DRM_SCHED_PRIORITY_NORMAL) > - return; > - > - mutex_lock(&ring->priority_mutex); > - /* something higher prio is executing, no need to decay */ > - if (ring->priority > priority) > - goto out_unlock; > - > - /* decay priority to the next level with a job available */ > - for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) { > - if (i == DRM_SCHED_PRIORITY_NORMAL > - || atomic_read(&ring->num_jobs[i])) { > - ring->priority = i; > - ring->funcs->set_priority(ring, i); > - break; > - } > - } > - > -out_unlock: > - mutex_unlock(&ring->priority_mutex); > -} > - > -/** > - * amdgpu_ring_priority_get - change the ring's priority > - * > - * @ring: amdgpu_ring structure holding the information > - * @priority: target priority > - * > - * Request a ring's priority to be raised to @priority (refcounted). > - */ > -void amdgpu_ring_priority_get(struct amdgpu_ring *ring, > - enum drm_sched_priority priority) > -{ > - if (!ring->funcs->set_priority) > - return; > - > - if (atomic_inc_return(&ring->num_jobs[priority]) <= 0) > - return; > - > - mutex_lock(&ring->priority_mutex); > - if (priority <= ring->priority) > - goto out_unlock; > - > - ring->priority = priority; > - ring->funcs->set_priority(ring, priority); > - > -out_unlock: > - mutex_unlock(&ring->priority_mutex); > -} > - > /** > * amdgpu_ring_init - init driver ring struct. > * > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > index 201c6ac7bf9d..a75e2418a20e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > @@ -167,9 +167,6 @@ struct amdgpu_ring_funcs { > uint32_t reg0, uint32_t reg1, > uint32_t ref, uint32_t mask); > void (*emit_tmz)(struct amdgpu_ring *ring, bool start); > - /* priority functions */ > - void (*set_priority) (struct amdgpu_ring *ring, > - enum drm_sched_priority priority); > /* Try to soft recover the ring to make the fence signal */ > void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); > int (*preempt_ib)(struct amdgpu_ring *ring); > @@ -259,10 +256,6 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, > uint32_t count); > void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib > *ib); > void amdgpu_ring_commit(struct amdgpu_ring *ring); > void amdgpu_ring_undo(struct amdgpu_ring *ring); > -void amdgpu_ring_priority_get(struct amdgpu_ring *ring, > - enum drm_sched_priority priority); > -void amdgpu_ring_priority_put(struct amdgpu_ring *ring, > - enum drm_sched_priority priority); > int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, > unsigned ring_size, struct amdgpu_irq_src *irq_src, > unsigned irq_type); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 05b6f01e1228..f5029eb9ac12 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -6275,104 +6275,6 @@ static void gfx_v8_0_ring_set_wptr_compute(struct > amdgpu_ring *ring) > WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); > } > > -static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring, > - bool acquire) > -{ > - struct amdgpu_device *adev = ring->adev; > - int pipe_num, tmp, reg; > - int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1; > - > - pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; > - > - /* first me only has 2 entries, GFX and HP3D */ > - if (ring->me > 0) > - pipe_num -= 2; > - > - reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num; > - tmp = RREG32(reg); > - tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent); > - WREG32(reg, tmp); > -} > - > -static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev, > - struct amdgpu_ring *ring, > - bool acquire) > -{ > - int i, pipe; > - bool reserve; > - struct amdgpu_ring *iring; > - > - mutex_lock(&adev->gfx.pipe_reserve_mutex); > - pipe = amdgpu_gfx_mec_queue_to_bit(adev, ring->me, ring->pipe, 0); > - if (acquire) > - set_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - else > - clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - > - if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, > AMDGPU_MAX_COMPUTE_QUEUES)) { > - /* Clear all reservations - everyone reacquires all resources */ > - for (i = 0; i < adev->gfx.num_gfx_rings; ++i) > - gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], > - true); > - > - for (i = 0; i < adev->gfx.num_compute_rings; ++i) > - > gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], > - true); > - } else { > - /* Lower all pipes without a current reservation */ > - for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { > - iring = &adev->gfx.gfx_ring[i]; > - pipe = amdgpu_gfx_mec_queue_to_bit(adev, > - iring->me, > - iring->pipe, > - 0); > - reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - gfx_v8_0_ring_set_pipe_percent(iring, reserve); > - } > - > - for (i = 0; i < adev->gfx.num_compute_rings; ++i) { > - iring = &adev->gfx.compute_ring[i]; > - pipe = amdgpu_gfx_mec_queue_to_bit(adev, > - iring->me, > - iring->pipe, > - 0); > - reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - gfx_v8_0_ring_set_pipe_percent(iring, reserve); > - } > - } > - > - mutex_unlock(&adev->gfx.pipe_reserve_mutex); > -} > - > -static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev, > - struct amdgpu_ring *ring, > - bool acquire) > -{ > - uint32_t pipe_priority = acquire ? 0x2 : 0x0; > - uint32_t queue_priority = acquire ? 0xf : 0x0; > - > - mutex_lock(&adev->srbm_mutex); > - vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); > - > - WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority); > - WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority); > - > - vi_srbm_select(adev, 0, 0, 0, 0); > - mutex_unlock(&adev->srbm_mutex); > -} > -static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring, > - enum drm_sched_priority priority) > -{ > - struct amdgpu_device *adev = ring->adev; > - bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW; > - > - if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) > - return; > - > - gfx_v8_0_hqd_set_priority(adev, ring, acquire); > - gfx_v8_0_pipe_reserve_resources(adev, ring, acquire); > -} > - > static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, > u64 addr, u64 seq, > unsigned flags) > @@ -7005,7 +6907,6 @@ static const struct amdgpu_ring_funcs > gfx_v8_0_ring_funcs_compute = { > .test_ib = gfx_v8_0_ring_test_ib, > .insert_nop = amdgpu_ring_insert_nop, > .pad_ib = amdgpu_ring_generic_pad_ib, > - .set_priority = gfx_v8_0_ring_set_priority_compute, > .emit_wreg = gfx_v8_0_ring_emit_wreg, > }; > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index ef263d075e06..a27b18d58aca 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -5130,105 +5130,6 @@ static u64 gfx_v9_0_ring_get_wptr_compute(struct > amdgpu_ring *ring) > return wptr; > } > > -static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring, > - bool acquire) > -{ > - struct amdgpu_device *adev = ring->adev; > - int pipe_num, tmp, reg; > - int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1; > - > - pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; > - > - /* first me only has 2 entries, GFX and HP3D */ > - if (ring->me > 0) > - pipe_num -= 2; > - > - reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num; > - tmp = RREG32(reg); > - tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent); > - WREG32(reg, tmp); > -} > - > -static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev, > - struct amdgpu_ring *ring, > - bool acquire) > -{ > - int i, pipe; > - bool reserve; > - struct amdgpu_ring *iring; > - > - mutex_lock(&adev->gfx.pipe_reserve_mutex); > - pipe = amdgpu_gfx_mec_queue_to_bit(adev, ring->me, ring->pipe, 0); > - if (acquire) > - set_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - else > - clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - > - if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, > AMDGPU_MAX_COMPUTE_QUEUES)) { > - /* Clear all reservations - everyone reacquires all resources */ > - for (i = 0; i < adev->gfx.num_gfx_rings; ++i) > - gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], > - true); > - > - for (i = 0; i < adev->gfx.num_compute_rings; ++i) > - > gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], > - true); > - } else { > - /* Lower all pipes without a current reservation */ > - for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { > - iring = &adev->gfx.gfx_ring[i]; > - pipe = amdgpu_gfx_mec_queue_to_bit(adev, > - iring->me, > - iring->pipe, > - 0); > - reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - gfx_v9_0_ring_set_pipe_percent(iring, reserve); > - } > - > - for (i = 0; i < adev->gfx.num_compute_rings; ++i) { > - iring = &adev->gfx.compute_ring[i]; > - pipe = amdgpu_gfx_mec_queue_to_bit(adev, > - iring->me, > - iring->pipe, > - 0); > - reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); > - gfx_v9_0_ring_set_pipe_percent(iring, reserve); > - } > - } > - > - mutex_unlock(&adev->gfx.pipe_reserve_mutex); > -} > - > -static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev, > - struct amdgpu_ring *ring, > - bool acquire) > -{ > - uint32_t pipe_priority = acquire ? 0x2 : 0x0; > - uint32_t queue_priority = acquire ? 0xf : 0x0; > - > - mutex_lock(&adev->srbm_mutex); > - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); > - > - WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority); > - WREG32_SOC15_RLC(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority); > - > - soc15_grbm_select(adev, 0, 0, 0, 0); > - mutex_unlock(&adev->srbm_mutex); > -} > - > -static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring, > - enum drm_sched_priority priority) > -{ > - struct amdgpu_device *adev = ring->adev; > - bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW; > - > - if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) > - return; > - > - gfx_v9_0_hqd_set_priority(adev, ring, acquire); > - gfx_v9_0_pipe_reserve_resources(adev, ring, acquire); > -} > - > static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) > { > struct amdgpu_device *adev = ring->adev; > @@ -6599,7 +6500,6 @@ static const struct amdgpu_ring_funcs > gfx_v9_0_ring_funcs_compute = { > .test_ib = gfx_v9_0_ring_test_ib, > .insert_nop = amdgpu_ring_insert_nop, > .pad_ib = amdgpu_ring_generic_pad_ib, > - .set_priority = gfx_v9_0_ring_set_priority_compute, > .emit_wreg = gfx_v9_0_ring_emit_wreg, > .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, > .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx