Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs
code with previous gfx generations from commit d6895ad39f3b39
("drm/amdgpu: resize VRAM BAR for CPU access v6").
Signed-off-by: Alan Swanson <rei...@improbability.net>
---
Unfortunately cannot test this with my RX5700 on my AMD X470
motherboard as its BIOS "Above 4G decoding" option does not
remap the PCI root bus. Trying "pci=nocrs" also unsuccessful.
However, I assume it's just absent due to missed commit
overlap during gfx10 bring up and should work.
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index edaa50d85..ba2b7ac0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -686,17 +686,23 @@ static void gmc_v10_0_vram_gtt_location(struct
amdgpu_device *adev,
*/
static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
{
- /* Could aper size report 0 ? */
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+ int r;
/* size in MB on si */
adev->gmc.mc_vram_size =
adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+
+ if (!(adev->flags & AMD_IS_APU)) {
+ r = amdgpu_device_resize_fb_bar(adev);
+ if (r)
+ return r;
+ }
+ adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
/* In case the PCI BAR is larger than the actual amount of vram */
+ adev->gmc.visible_vram_size = adev->gmc.aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
--
2.26.2
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