Instead of having each for smu v11 and v12.
Change-Id: Ic459c5ea4e047dd13a0e6873c83e1e87ca456d10
Signed-off-by: Evan Quan <evan.q...@amd.com>
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 +--
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 --
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 --
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 +--
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 4 +--
drivers/gpu/drm/amd/powerplay/smu_cmn.c | 30 ++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smu_cmn.h | 4 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 31 +------------------
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 23 --------------
10 files changed, 42 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index baf02a74efb6..1fb221c0cce7 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1823,7 +1823,7 @@ static bool arcturus_is_dpm_running(struct smu_context
*smu)
int ret = 0;
uint32_t feature_mask[2];
unsigned long feature_enabled;
- ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
@@ -2273,7 +2273,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
.init_display_count = NULL,
.set_allowed_mask = smu_v11_0_set_allowed_mask,
- .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .get_enabled_mask = smu_cmn_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.notify_display_change = NULL,
.set_power_limit = smu_v11_0_set_power_limit,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index df4d7633b04b..70274552e3af 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -180,9 +180,6 @@ int smu_v11_0_init_display_count(struct smu_context *smu,
uint32_t count);
int smu_v11_0_set_allowed_mask(struct smu_context *smu);
-int smu_v11_0_get_enabled_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num);
-
int smu_v11_0_notify_display_change(struct smu_context *smu);
int smu_v11_0_get_current_power_limit(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 20652b38f96d..dd3904e8aef0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -64,9 +64,6 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu);
int smu_v12_0_set_default_dpm_tables(struct smu_context *smu);
-int smu_v12_0_get_enabled_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num);
-
int smu_v12_0_mode2_reset(struct smu_context *smu);
int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum
smu_clk_type clk_type,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 6d3ddb6203f8..3cf8eebd8247 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1320,7 +1320,7 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
int ret = 0;
uint32_t feature_mask[2];
unsigned long feature_enabled;
- ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
@@ -2298,7 +2298,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
.init_display_count = smu_v11_0_init_display_count,
.set_allowed_mask = smu_v11_0_set_allowed_mask,
- .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .get_enabled_mask = smu_cmn_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.notify_display_change = smu_v11_0_notify_display_change,
.set_power_limit = smu_v11_0_set_power_limit,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 1d40795b27e6..521ab71d1ee8 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -989,7 +989,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.init_smc_tables = smu_v12_0_init_smc_tables,
.fini_smc_tables = smu_v12_0_fini_smc_tables,
.set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
- .get_enabled_mask = smu_v12_0_get_enabled_mask,
+ .get_enabled_mask = smu_cmn_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
.mode2_reset = smu_v12_0_mode2_reset,
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index c91aec90ce32..8431b6ac3e3d 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1113,7 +1113,7 @@ static bool sienna_cichlid_is_dpm_running(struct
smu_context *smu)
int ret = 0;
uint32_t feature_mask[2];
unsigned long feature_enabled;
- ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
@@ -2417,7 +2417,7 @@ static const struct pptable_funcs
sienna_cichlid_ppt_funcs = {
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
.init_display_count = NULL,
.set_allowed_mask = smu_v11_0_set_allowed_mask,
- .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .get_enabled_mask = smu_cmn_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.notify_display_change = NULL,
.set_power_limit = smu_v11_0_set_power_limit,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_cmn.c
b/drivers/gpu/drm/amd/powerplay/smu_cmn.c
index 24aabca5739e..4a8511c1051f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_cmn.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_cmn.c
@@ -162,3 +162,33 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
return ret;
}
+
+int smu_cmn_get_enabled_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num)
+{
+ uint32_t feature_mask_high = 0, feature_mask_low = 0;
+ struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+
+ if (!feature_mask || num < 2)
+ return -EINVAL;
+
+ if (bitmap_empty(feature->enabled, feature->feature_num)) {
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh,
&feature_mask_high);
+ if (ret)
+ return ret;
+
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow,
&feature_mask_low);
+ if (ret)
+ return ret;
+
+ feature_mask[0] = feature_mask_low;
+ feature_mask[1] = feature_mask_high;
+ } else {
+ bitmap_copy((unsigned long *)feature_mask, feature->enabled,
+ feature->feature_num);
+ }
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_cmn.h
b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
index c28ea4df4b32..fc271aa7d39c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_cmn.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
@@ -35,4 +35,8 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
int smu_cmn_feature_is_enabled(struct smu_context *smu,
enum smu_feature_mask mask);
+int smu_cmn_get_enabled_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num);
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f1880f257237..efe77c87dad0 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -871,35 +871,6 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)
return ret;
}
-int smu_v11_0_get_enabled_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
-{
- uint32_t feature_mask_high = 0, feature_mask_low = 0;
- struct smu_feature *feature = &smu->smu_feature;
- int ret = 0;
-
- if (!feature_mask || num < 2)
- return -EINVAL;
-
- if (bitmap_empty(feature->enabled, feature->feature_num)) {
- ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh,
&feature_mask_high);
- if (ret)
- return ret;
-
- ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow,
&feature_mask_low);
- if (ret)
- return ret;
-
- feature_mask[0] = feature_mask_low;
- feature_mask[1] = feature_mask_high;
- } else {
- bitmap_copy((unsigned long *)feature_mask, feature->enabled,
- feature->feature_num);
- }
-
- return ret;
-}
-
int smu_v11_0_system_features_control(struct smu_context *smu,
bool en)
{
@@ -916,7 +887,7 @@ int smu_v11_0_system_features_control(struct smu_context
*smu,
bitmap_zero(feature->supported, feature->feature_num);
if (en) {
- ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 7286edec2789..33ec9fc44f4c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -296,29 +296,6 @@ int smu_v12_0_set_default_dpm_tables(struct smu_context
*smu)
return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
-int smu_v12_0_get_enabled_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
-{
- uint32_t feature_mask_high = 0, feature_mask_low = 0;
- int ret = 0;
-
- if (!feature_mask || num < 2)
- return -EINVAL;
-
- ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh,
&feature_mask_high);
- if (ret)
- return ret;
-
- ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow,
&feature_mask_low);
- if (ret)
- return ret;
-
- feature_mask[0] = feature_mask_low;
- feature_mask[1] = feature_mask_high;
-
- return ret;
-}
-
int smu_v12_0_mode2_reset(struct smu_context *smu){
return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
SMU_RESET_MODE_2, NULL);
}
--
2.27.0
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