No,  the change below is not a good idea.
-#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || 
defined(SWSMU_CODE_LAYER_L4)
+#if defined(SWSMU_CODE_LAYER_L1) || defined(SWSMU_CODE_LAYER_L2) || 
+defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
These are used to guard a clear code layer. I recently just cleaned up the code 
layer mess ups(which produced lots of redundant codes and made lock protection 
a disaster).

To this specific one, whether or not to use smu_cmn API should be decided at 
ASIC level(${asic}_ppt.c).
Each ASIC can have its own implementation or to use smu v11/v12 common API or 
even smu_cmn api(shared by all ASICs).
But all of these should be decided at ASIC level.

P.S. Likun sent out a patch which should fix the issue here.

BR,
Evan
-----Original Message-----
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Feng, Kenneth
Sent: Wednesday, July 22, 2020 4:12 PM
To: Zhu, Changfeng <changfeng....@amd.com>; amd-gfx@lists.freedesktop.org; 
Huang, Ray <ray.hu...@amd.com>
Subject: RE: [PATCH] Revert "drm/amd/powerplay: drop unnecessary message 
support check"

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng <kenneth.f...@amd.com>


-----Original Message-----
From: Zhu, Changfeng <changfeng....@amd.com> 
Sent: Wednesday, July 22, 2020 4:01 PM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth <kenneth.f...@amd.com>; Huang, 
Ray <ray.hu...@amd.com>
Cc: Zhu, Changfeng <changfeng....@amd.com>
Subject: [PATCH] Revert "drm/amd/powerplay: drop unnecessary message support 
check"

From: changzhu <changfeng....@amd.com>

From: Changfeng <changfeng....@amd.com>

The below 3 messages are not supported on Renoir SMU_MSG_PrepareMp1ForShutdown 
SMU_MSG_PrepareMp1ForUnload SMU_MSG_PrepareMp1ForReset

It needs to revert patch:
drm/amd/powerplay: drop unnecessary message support check to avoid set mp1 
state fail during gpu reset on renoir.

Change-Id: Ib34d17ab88e1c88173827cca962d8154ad883ab7
Signed-off-by: changfeng <changfeng....@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++++++++
 drivers/gpu/drm/amd/powerplay/smu_cmn.h    | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 838a369c9ec3..f778b00e49eb 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -34,6 +34,7 @@
 #include "sienna_cichlid_ppt.h"
 #include "renoir_ppt.h"
 #include "amd_pcie.h"
+#include "smu_cmn.h"
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -1589,6 +1590,14 @@ int smu_set_mp1_state(struct smu_context *smu,
                return 0;
        }
 
+       /* some asics may not support those messages */
+       if (smu_cmn_to_asic_specific_index(smu,
+                                          CMN2ASIC_MAPPING_MSG,
+                                          msg) < 0) {
+               mutex_unlock(&smu->mutex);
+               return 0;
+       }
+
        ret = smu_send_smc_msg(smu, msg, NULL);
        if (ret)
                dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n"); diff --git 
a/drivers/gpu/drm/amd/powerplay/smu_cmn.h 
b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
index 98face8c5fd6..f9e63f18b157 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_cmn.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
@@ -25,7 +25,7 @@
 
 #include "amdgpu_smu.h"
 
-#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || 
defined(SWSMU_CODE_LAYER_L4)
+#if defined(SWSMU_CODE_LAYER_L1) || defined(SWSMU_CODE_LAYER_L2) || 
+defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
                                    enum smu_message_type msg,
                                    uint32_t param,
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cevan.quan%40amd.com%7C8105bfba31de4bb7bc7f08d82e16e403%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310023202564830&amp;sdata=U0HuFMHcmQ6ZtPsdL%2FisRBIvR9J422uydwWuDOY%2BYF4%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to