[AMD Public Use]
Reviewed-by: Guchun Chen <guchun.c...@amd.com>
Regards,
Guchun
-----Original Message-----
From: Zhang, Morris <shiwu.zh...@amd.com>
Sent: Monday, August 10, 2020 1:15 PM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking <hawking.zh...@amd.com>;
Chen, Guchun <guchun.c...@amd.com>
Cc: Zhang, Morris <shiwu.zh...@amd.com>
Subject: [PATCH] drm/amdgpu: update gc golden register for arcturus
Update golden setting to improve performance on HPC and ML apps
Signed-off-by: shiwu.zhang <shiwu.zh...@amd.com>
Tested-by: gang.long <gang.l...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 294c1ca2bc97..b5a6ab1a1cc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -691,6 +691,7 @@ static const struct soc15_reg_golden
golden_settings_gc_9_4_1_arct[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000,
+0x30000000)
};
static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {
--
2.17.1
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