[AMD Public Use]
It's preferred to have braces if the else has a single line:
https://www.kernel.org/doc/html/v4.10/process/coding-style.html#placing-braces-and-spaces
Right above "3.1) Spaces"
Kent
> -----Original Message-----
> From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Zhang,
> Hawking
> Sent: Friday, September 18, 2020 8:07 AM
> To: Koenig, Christian <christian.koe...@amd.com>;
> amd-gfx@lists.freedesktop.org;
> Deucher, Alexander <alexander.deuc...@amd.com>; Wang, Kevin(Yang)
> <kevin1.w...@amd.com>; Chen, Guchun <guchun.c...@amd.com>
> Subject: RE: [PATCH 3/3] drm/amdgpu: support indirect access reg outside of
> mmio bar (v2)
>
> [AMD Public Use]
>
> > + } else
>
> RE - This should use "} else {". Apart from that looks good to me.
>
> Hi Chris,
>
> Since there is only one line under "else", I dropped the "{}". I thought that
> is okay in current
> kernel coding style and checkpatch.pl also shows no complain.
>
> So you mean you want the code to be the following?
>
> } else {
> ret = adev->pcie_rreg(adev, reg * 4);
> }
>
> I can make the change anyway. Does that mean I can get your RB with coding
> style change
> for the series?
>
> Regards,
> Hawking
>
>
> -----Original Message-----
> From: Christian König <ckoenig.leichtzumer...@gmail.com>
> Sent: Friday, September 18, 2020 19:27
> To: Zhang, Hawking <hawking.zh...@amd.com>; amd-gfx@lists.freedesktop.org;
> Deucher,
> Alexander <alexander.deuc...@amd.com>; Wang, Kevin(Yang)
> <kevin1.w...@amd.com>; Koenig, Christian <christian.koe...@amd.com>; Chen,
> Guchun
> <guchun.c...@amd.com>
> Subject: Re: [PATCH 3/3] drm/amdgpu: support indirect access reg outside of
> mmio bar (v2)
>
> Am 18.09.20 um 11:51 schrieb Hawking Zhang:
> > support both direct and indirect accessor in unified helper functions.
> >
> > v2: Retire indirect mmio access via mm_index/data
> >
> > Signed-off-by: Hawking Zhang <hawking.zh...@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 23 +++----
> > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 96
> > +++++++++++------------------
> > drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 4 +-
> > 4 files changed, 51 insertions(+), 74 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 40ee44b..50341f0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -1019,12 +1019,13 @@ int amdgpu_gpu_wait_for_idle(struct
> > amdgpu_device *adev);
> >
> > void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
> > uint32_t *buf, size_t size, bool write);
> > -uint32_t
> > amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> > +uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
> > + uint32_t reg, uint32_t acc_flags); void
> > +amdgpu_device_wreg(struct amdgpu_device *adev,
> > + uint32_t reg, uint32_t v,
> > uint32_t acc_flags);
> > -void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> > - uint32_t acc_flags);
> > -void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg,
> > uint32_t v,
> > - uint32_t acc_flags);
> > +void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
> > + uint32_t reg, uint32_t v);
> > void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t
> > value);
> > uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t
> > offset);
> >
> > @@ -1054,8 +1055,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
> > */
> > #define AMDGPU_REGS_NO_KIQ (1<<1)
> >
> > -#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg),
> > AMDGPU_REGS_NO_KIQ) -#define WREG32_NO_KIQ(reg, v)
> > amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
> > +#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg),
> > +AMDGPU_REGS_NO_KIQ) #define WREG32_NO_KIQ(reg, v)
> > +amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
> >
> > #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
> > #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) @@
> > -1063,9 +1064,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
> > #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
> > #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
> >
> > -#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) -#define
> > DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n",
> > amdgpu_mm_rreg(adev, (reg), 0)) -#define WREG32(reg, v)
> > amdgpu_mm_wreg(adev, (reg), (v), 0)
> > +#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) #define
> > +DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n",
> > +amdgpu_device_rreg(adev, (reg), 0)) #define WREG32(reg, v)
> > +amdgpu_device_wreg(adev, (reg), (v), 0)
> > #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
> > #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
> > #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) @@ -1111,7
> > +1112,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
> > WREG32_SMC(_Reg, tmp); \
> > } while (0)
> >
> > -#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " :
> > 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
> > +#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " :
> > +0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
> > #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
> > #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > index abe0c27..2d125b8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > @@ -267,7 +267,7 @@ static int amdgpu_debugfs_process_reg_op(bool read,
> > struct file
> *f,
> > } else {
> > r = get_user(value, (uint32_t *)buf);
> > if (!r)
> > - amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value,
> > 0);
> > + amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);
> > }
> > if (r) {
> > result = r;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 77785b2..beef764 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -303,10 +303,10 @@ void amdgpu_device_vram_access(struct amdgpu_device
> *adev, loff_t pos,
> > }
> >
> > /*
> > - * MMIO register access helper functions.
> > + * register access helper functions.
> > */
> > /**
> > - * amdgpu_mm_rreg - read a memory mapped IO register
> > + * amdgpu_device_rreg - read a memory mapped IO or indirect register
> > *
> > * @adev: amdgpu_device pointer
> > * @reg: dword aligned register offset @@ -314,33 +314,27 @@ void
> > amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
> > *
> > * Returns the 32 bit value from the offset specified.
> > */
> > -uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> > - uint32_t acc_flags)
> > +uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
> > + uint32_t reg, uint32_t acc_flags)
> > {
> > uint32_t ret;
> >
> > if (adev->in_pci_err_recovery)
> > return 0;
> >
> > - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev) &&
> > - down_read_trylock(&adev->reset_sem)) {
> > - ret = amdgpu_kiq_rreg(adev, reg);
> > - up_read(&adev->reset_sem);
> > - return ret;
> > - }
> > -
> > - if ((reg * 4) < adev->rmmio_size)
> > - ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
> > - else {
> > - unsigned long flags;
> > + if ((reg * 4) < adev->rmmio_size) {
> > + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
> > + amdgpu_sriov_runtime(adev) &&
> > + down_read_trylock(&adev->reset_sem)) {
> > + ret = amdgpu_kiq_rreg(adev, reg);
> > + up_read(&adev->reset_sem);
> > + } else
> > + ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
> > + } else
>
> This should use "} else {". Apart from that looks good to me.
>
> Christian.
>
> > + ret = adev->pcie_rreg(adev, reg * 4);
> >
> > - spin_lock_irqsave(&adev->mmio_idx_lock, flags);
> > - writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX *
> > 4));
> > - ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
> > - spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
> > - }
> > + trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
> >
> > - trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
> > return ret;
> > }
> >
> > @@ -394,29 +388,8 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev,
> > uint32_t
> offset, uint8_t value)
> > BUG();
> > }
> >
> > -static inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
> > - uint32_t reg, uint32_t v,
> > - uint32_t acc_flags)
> > -{
> > - if (adev->in_pci_err_recovery)
> > - return;
> > -
> > - trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
> > -
> > - if ((reg * 4) < adev->rmmio_size)
> > - writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> > - else {
> > - unsigned long flags;
> > -
> > - spin_lock_irqsave(&adev->mmio_idx_lock, flags);
> > - writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX *
> > 4));
> > - writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
> > - spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
> > - }
> > -}
> > -
> > /**
> > - * amdgpu_mm_wreg - write to a memory mapped IO register
> > + * amdgpu_device_wreg - write to a memory mapped IO or indirect
> > + register
> > *
> > * @adev: amdgpu_device pointer
> > * @reg: dword aligned register offset @@ -425,20 +398,25 @@ static
> > inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
> > *
> > * Writes the value specified to the offset specified.
> > */
> > -void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> > - uint32_t acc_flags)
> > +void amdgpu_device_wreg(struct amdgpu_device *adev,
> > + uint32_t reg, uint32_t v,
> > + uint32_t acc_flags)
> > {
> > if (adev->in_pci_err_recovery)
> > return;
> >
> > - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev) &&
> > - down_read_trylock(&adev->reset_sem)) {
> > - amdgpu_kiq_wreg(adev, reg, v);
> > - up_read(&adev->reset_sem);
> > - return;
> > - }
> > + if ((reg * 4) < adev->rmmio_size) {
> > + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
> > + amdgpu_sriov_runtime(adev) &&
> > + down_read_trylock(&adev->reset_sem)) {
> > + amdgpu_kiq_wreg(adev, reg, v);
> > + up_read(&adev->reset_sem);
> > + } else
> > + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> > + } else
> > + adev->pcie_wreg(adev, reg * 4, v);
> >
> > - amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);
> > + trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
> > }
> >
> > /*
> > @@ -446,21 +424,19 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev,
> > uint32_t
> reg, uint32_t v,
> > *
> > * this function is invoked only the debugfs register access
> > * */
> > -void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg,
> > uint32_t v,
> > - uint32_t acc_flags)
> > +void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
> > + uint32_t reg, uint32_t v)
> > {
> > if (adev->in_pci_err_recovery)
> > return;
> >
> > if (amdgpu_sriov_fullaccess(adev) &&
> > - adev->gfx.rlc.funcs &&
> > - adev->gfx.rlc.funcs->is_rlcg_access_range) {
> > -
> > + adev->gfx.rlc.funcs &&
> > + adev->gfx.rlc.funcs->is_rlcg_access_range) {
> > if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> > return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
> > - }
> > -
> > - amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags);
> > + } else
> > + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> > }
> >
> > /**
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > index 63e734a..5da20fc 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > @@ -35,7 +35,7 @@
> > #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
> >
> > job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence-
> > >finished)
> >
> > -TRACE_EVENT(amdgpu_mm_rreg,
> > +TRACE_EVENT(amdgpu_device_rreg,
> > TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
> > TP_ARGS(did, reg, value),
> > TP_STRUCT__entry(
> > @@ -54,7 +54,7 @@ TRACE_EVENT(amdgpu_mm_rreg,
> > (unsigned long)__entry->value)
> > );
> >
> > -TRACE_EVENT(amdgpu_mm_wreg,
> > +TRACE_EVENT(amdgpu_device_wreg,
> > TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
> > TP_ARGS(did, reg, value),
> > TP_STRUCT__entry(
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