Add xgmi perfmons for Arcturus.
Signed-off-by: Jonathan Kim <jonathan....@amd.com>
v3: Align with patch 2 streamlining perf types versus event config types.
v2: Resend for re-review with alignment for v3 in patch 2.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 43 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 3 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
index 610f96bb0239..5f6de18cfee2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -35,6 +35,9 @@
#define NUM_EVENT_TYPES_VEGA20 1
#define NUM_EVENTS_VEGA20_XGMI 2
#define NUM_EVENTS_VEGA20_MAX NUM_EVENTS_VEGA20_XGMI
+#define NUM_EVENT_TYPES_ARCTURUS 1
+#define NUM_EVENTS_ARCTURUS_XGMI 6
+#define NUM_EVENTS_ARCTURUS_MAX NUM_EVENTS_ARCTURUS_XGMI
struct amdgpu_pmu_event_attribute {
struct device_attribute attr;
@@ -122,6 +125,21 @@ static const char
*df_vega20_events[NUM_EVENTS_DF_VEGA20][2] = {
{ "cake1_ftiinstat_rspalloc", "event=0xb,instance=0x47,umask=0x8" },
};
+/* Arcturus events */
+static const char *arcturus_events[NUM_EVENTS_ARCTURUS_MAX][2] = {
+ { "xgmi_link0_data_outbound", "event=0x7,instance=0x4b,umask=0x2" },
+ { "xgmi_link1_data_outbound", "event=0x7,instance=0x4c,umask=0x2" },
+ { "xgmi_link2_data_outbound", "event=0x7,instance=0x4d,umask=0x2" },
+ { "xgmi_link3_data_outbound", "event=0x7,instance=0x4e,umask=0x2" },
+ { "xgmi_link4_data_outbound", "event=0x7,instance=0x4f,umask=0x2" },
+ { "xgmi_link5_data_outbound", "event=0x7,instance=0x50,umask=0x2" }
+};
+
+static const int arcturus_event_config_types[NUM_EVENT_TYPES_ARCTURUS][2] = {
+ { AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI, NUM_EVENTS_ARCTURUS_XGMI }
+};
+
+
/* initialize perf counter */
static int amdgpu_perf_event_init(struct perf_event *event)
{
@@ -553,6 +571,31 @@ int amdgpu_pmu_init(struct amdgpu_device *adev)
}
break;
+ case CHIP_ARCTURUS:
+ pmu_entry = kzalloc(sizeof(struct amdgpu_pmu_entry),
+ GFP_KERNEL);
+
+ if (!pmu_entry)
+ return -ENOMEM;
+
+ pmu_entry->adev = adev;
+ pmu_entry->fmt_attr_group.name = "format";
+ pmu_entry->fmt_attr_group.attrs = NULL;
+ pmu_entry->evt_attr_group.name = "events";
+ pmu_entry->evt_attr_group.attrs = NULL;
+ ret = init_pmu_by_type(pmu_entry, "", "amdgpu",
+ AMDGPU_PMU_PERF_TYPE_ALL,
+ amdgpu_pmu_formats,
+ NUM_FORMATS_AMDGPU_PMU,
+ arcturus_events,
+ NUM_EVENTS_ARCTURUS_MAX,
+ arcturus_event_config_types,
+ NUM_EVENT_TYPES_ARCTURUS);
+
+ if (ret)
+ kfree(pmu_entry);
+ break;
+
default:
return 0;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 6e57ae95f997..6b4b30a8dce5 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -513,6 +513,7 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev,
uint64_t config,
switch (adev->asic_type) {
case CHIP_VEGA20:
+ case CHIP_ARCTURUS:
if (is_add)
return df_v3_6_pmc_add_cntr(adev, config);
@@ -554,6 +555,7 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev,
uint64_t config,
switch (adev->asic_type) {
case CHIP_VEGA20:
+ case CHIP_ARCTURUS:
ret = df_v3_6_pmc_get_ctrl_settings(adev,
config,
counter_idx,
@@ -590,6 +592,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device
*adev,
switch (adev->asic_type) {
case CHIP_VEGA20:
+ case CHIP_ARCTURUS:
df_v3_6_pmc_get_read_settings(adev, config, counter_idx,
&lo_base_addr, &hi_base_addr);
--
2.17.1
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