From: Tao Zhou <tao.zh...@amd.com>
Same as navy_flounder.
Signed-off-by: Tao Zhou <tao.zh...@amd.com>
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>
Reviewed-by: Jiansong Chen <jiansong.c...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index bde63e7cd501..d535dfa84bdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -763,6 +763,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
+ case CHIP_DIMGREY_CAVEFISH:
default:
adev->gmc.gart_size = 512ULL << 20;
break;
@@ -829,6 +830,7 @@ static int gmc_v10_0_sw_init(void *handle)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
+ case CHIP_DIMGREY_CAVEFISH:
adev->num_vmhubs = 2;
/*
* To fulfill 4-level page support,
@@ -943,6 +945,7 @@ static void gmc_v10_0_init_golden_registers(struct
amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
+ case CHIP_DIMGREY_CAVEFISH:
break;
default:
break;
--
2.25.4
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