[PATCH 36/40] drm/amd/pm: fulfill the Polaris implementation for get_clock_by_type_with_latency()

[Evan Quan]

Fulfill Polaris get_clock_by_type_with_latency().

Change-Id: I143959f9fcb218a74aabb2fbf6cd6c7b2f0716f1
Signed-off-by: Evan Quan <evan.q...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
---
 .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 59c199cd7aeb..3700352286c5 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -5041,6 +5041,72 @@ static int smu7_get_clock_by_type(struct pp_hwmgr 
*hwmgr, enum amd_pp_clock_type
        return 0;
 }
 
+static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr,
+                                      struct pp_clock_levels_with_latency 
*clocks)
+{
+       struct phm_ppt_v1_information *table_info =
+                       (struct phm_ppt_v1_information *)hwmgr->pptable;
+       struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
+                       table_info->vdd_dep_on_sclk;
+       int i;
+
+       clocks->num_levels = 0;
+       for (i = 0; i < dep_sclk_table->count; i++) {
+               if (dep_sclk_table->entries[i].clk) {
+                       clocks->data[clocks->num_levels].clocks_in_khz =
+                               dep_sclk_table->entries[i].clk * 10;
+                       clocks->num_levels++;
+               }
+       }
+
+       return 0;
+}
+
+static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr,
+                                      struct pp_clock_levels_with_latency 
*clocks)
+{
+       struct phm_ppt_v1_information *table_info =
+                       (struct phm_ppt_v1_information *)hwmgr->pptable;
+       struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
+                       table_info->vdd_dep_on_mclk;
+       int i;
+
+       clocks->num_levels = 0;
+       for (i = 0; i < dep_mclk_table->count; i++) {
+               if (dep_mclk_table->entries[i].clk) {
+                       clocks->data[clocks->num_levels].clocks_in_khz =
+                                       dep_mclk_table->entries[i].clk * 10;
+                       clocks->data[clocks->num_levels].latency_in_us =
+                                       smu7_get_mem_latency(hwmgr, 
dep_mclk_table->entries[i].clk);
+                       clocks->num_levels++;
+               }
+       }
+
+       return 0;
+}
+
+static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
+                                              enum amd_pp_clock_type type,
+                                              struct 
pp_clock_levels_with_latency *clocks)
+{
+       if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
+             hwmgr->chip_id <= CHIP_VEGAM))
+               return -EINVAL;
+
+       switch (type) {
+       case amd_pp_sys_clock:
+               smu7_get_sclks_with_latency(hwmgr, clocks);
+               break;
+       case amd_pp_mem_clock:
+               smu7_get_mclks_with_latency(hwmgr, clocks);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
                                        uint32_t virtual_addr_low,
                                        uint32_t virtual_addr_hi,
@@ -5458,6 +5524,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
        .get_mclk_od = smu7_get_mclk_od,
        .set_mclk_od = smu7_set_mclk_od,
        .get_clock_by_type = smu7_get_clock_by_type,
+       .get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency,
        .read_sensor = smu7_read_sensor,
        .dynamic_state_management_disable = smu7_disable_dpm_tasks,
        .avfs_control = smu7_avfs_control,
-- 
2.28.0

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