[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Jiansong Chen <jiansong.c...@amd.com>
-----Original Message-----
From: Zhou1, Tao <tao.zh...@amd.com>
Sent: Friday, November 27, 2020 12:28 PM
To: Chen, Jiansong (Simon) <jiansong.c...@amd.com>; Gui, Jack
<jack....@amd.com>; Zhang, Hawking <hawking.zh...@amd.com>;
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <tao.zh...@amd.com>
Subject: [PATCH] drm/amdgpu: update GC golden setting for dimgrey_cavefish
Update GC golden setting for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 841d39eb62d9..ffbda6680a68 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3266,6 +3266,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_vangogh[] =
static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000,
+0x78000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
--
2.17.1
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