Am 02.07.21 um 05:23 schrieb Peng Ju Zhou:
From: "Emily.Deng" <emily.d...@amd.com>
After FLR, the msix will be cleared, so need to re-enable it.
Signed-off-by: Emily.Deng <emily.d...@amd.com>
Signed-off-by: Peng Ju Zhou <pengju.z...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 90f50561b43a..034420c38352 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -277,6 +277,19 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
return true;
}
+void amdgpu_restore_msix(struct amdgpu_device *adev)
I think this function should be static and maybe add a one line comment
like "Clear and re-set the MSIX flags if they where set before to
trigger re-enabling it".
With that done feel free to add an Acked-by: Christian König
<christian.koe...@amd.com>, but I would also wait what Alex has to say
about that.
Regards,
Christian
+{
+ u16 ctrl;
+
+ pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS,
&ctrl);
+ if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))
+ return;
+
+ ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
+ pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
PCI_MSIX_FLAGS, ctrl);
+ ctrl |= PCI_MSIX_FLAGS_ENABLE;
+ pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
PCI_MSIX_FLAGS, ctrl);
+}
/**
* amdgpu_irq_init - initialize interrupt handling
*
@@ -558,6 +571,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
amdgpu_device *adev)
{
int i, j, k;
+ amdgpu_restore_msix(adev);
for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
continue;
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