RE: [PATCH] drm/amdgpu: return error type when programing registers fails

[Chen, Guchun]

[Public]

+                       if (tmp & INTERFACE_NOT_ENABLED_FLAG)
+                               error_type = RLCG_INTERFACE_NOT_ENABLED;
+                       if (tmp & WRONG_OPERATION_TYPE_FLAG)
+                               error_type = RLCG_WRONG_OPERATION_TYPE;
+                       if (tmp & NOT_IN_RANGE_FLAG)
+                               error_type = RLCG_NOT_IN_RANGE;

Is it possbile that in current code logic, when tmp = 
INTERFACE_NOT_ENABLED_FLAG | WRONG_OPERATION_TYPE_FLAG | NOT_IN_RANGE_FLAG, 
error_type will be overwritten twice, and set to RLCG_NOT_IN_RANGE finally.

Regards,
Guchun

-----Original Message-----
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Roy Sun
Sent: Thursday, July 8, 2021 6:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Sun, Roy <roy....@amd.com>
Subject: [PATCH] drm/amdgpu: return error type when programing registers fails

Signed-off-by: Roy Sun <roy....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bc4347a72301..2ec5b973a888 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,6 +56,15 @@
 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid     1
 #define GFX10_MEC_HPD_SIZE     2048
 
+#define INTERFACE_NOT_ENABLED_FLAG     0x4000000
+#define WRONG_OPERATION_TYPE_FLAG      0x2000000
+#define NOT_IN_RANGE_FLAG      0x1000000
+
+#define RLCG_UNKNOWN_TYPE      0
+#define RLCG_INTERFACE_NOT_ENABLED     1
+#define RLCG_WRONG_OPERATION_TYPE      2
+#define RLCG_NOT_IN_RANGE      3
+
 #define F32_CE_PROGRAM_RAM_SIZE                65536
 #define RLCG_UCODE_LOADING_START_ADDRESS       0x00002000L
 
@@ -1533,8 +1542,17 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
                        udelay(10);
                }
 
-               if (i >= retries)
-                       pr_err("timeout: rlcg program reg:0x%05x failed !\n", 
offset);
+               if (i >= retries) {
+                       u32 error_type = RLCG_UNKNOWN_TYPE;
+
+                       if (tmp & INTERFACE_NOT_ENABLED_FLAG)
+                               error_type = RLCG_INTERFACE_NOT_ENABLED;
+                       if (tmp & WRONG_OPERATION_TYPE_FLAG)
+                               error_type = RLCG_WRONG_OPERATION_TYPE;
+                       if (tmp & NOT_IN_RANGE_FLAG)
+                               error_type = RLCG_NOT_IN_RANGE;
+                       pr_err("timeout: rlcg program reg:0x%05x failed! Error 
type: %d.\n", offset, error_type);
+               }
        }
 
        ret = readl(scratch_reg0);
-- 
2.32.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cguchun.chen%40amd.com%7C99ca80d6566d4a09dabe08d941fa1578%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637613364637870490%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=FVx31FaVzTZ30a3IJi4YM1IMu%2BqKGxP0bmU5qzGVh5E%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx