On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai <aurabindo.pil...@amd.com> wrote: > > [Why & How] > The DCN3 SoC parameter num_states was calculated but not saved into the > object. > > Signed-off-by: Aurabindo Pillai <aurabindo.pil...@amd.com> > Cc: sta...@vger.kernel.org
Please add: Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 to the series. With that fixed, series is: Acked-by: Alex Deucher <alexander.deuc...@amd.com> > --- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c > index 1333f0541f1b..43ac6f42dd80 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c > @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct > clk_bw_params *bw_params > dram_speed_mts[num_states++] = > bw_params->clk_table.entries[j++].memclk_mhz * 16; > } > > + dcn3_0_soc.num_states = num_states; > for (i = 0; i < dcn3_0_soc.num_states; i++) { > dcn3_0_soc.clock_limits[i].state = i; > dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; > -- > 2.30.2 >
