From: Wenjing Liu <wenjing....@amd.com>
[why]
option 1: disallow different lanes to have different lane settings
option 2: dpcd lane settings will always use the same hw lane settings
even if it doesn't match requested lane adjust
Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Anson Jacob <anson.ja...@amd.com>
Signed-off-by: Wenjing Liu <wenjing....@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 18 ++++++++++++------
.../amd/display/include/link_service_types.h | 6 +++++-
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index f13bf8ca93aa..f55dac1c7ea1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -733,12 +733,16 @@ void dp_decide_lane_settings(
#endif
}
- /*
- * We find the maximum of the requested settings across all lanes
- * and set this maximum for all lanes
- */
- maximize_lane_settings(hw_lane_settings);
dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings,
dpcd_lane_settings);
+
+ if (lt_settings->disallow_per_lane_settings) {
+ /* we find the maximum of the requested settings across all
lanes*/
+ /* and set this maximum for all lanes*/
+ maximize_lane_settings(hw_lane_settings);
+ if (lt_settings->always_match_dpcd_with_hw_lane_settings)
+ dp_hw_to_dpcd_lane_settings(lt_settings,
hw_lane_settings, dpcd_lane_settings);
+ }
+
}
static uint8_t get_nibble_at_index(const uint8_t *buf,
@@ -1455,6 +1459,8 @@ static inline void decide_8b_10b_training_settings(
lt_settings->pattern_for_eq = decide_eq_training_pattern(link,
link_setting);
lt_settings->enhanced_framing = 1;
lt_settings->should_set_fec_ready = true;
+ lt_settings->disallow_per_lane_settings = true;
+ lt_settings->always_match_dpcd_with_hw_lane_settings = true;
dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings,
lt_settings->dpcd_lane_settings);
}
@@ -1481,6 +1487,7 @@ static inline void
decide_128b_132b_training_settings(struct dc_link *link,
link->dpcd_caps.lttpr_caps.phy_repeater_cnt) + 1) *
20000;
lt_settings->lttpr_mode =
dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) ?
LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_TRANSPARENT;
+ lt_settings->disallow_per_lane_settings = true;
dp_hw_to_dpcd_lane_settings(lt_settings,
lt_settings->hw_lane_settings,
lt_settings->dpcd_lane_settings);
}
@@ -3593,7 +3600,6 @@ static void dp_test_send_phy_test_pattern(struct dc_link
*link)
dp_hw_to_dpcd_lane_settings(&link_training_settings,
link_training_settings.hw_lane_settings,
link_training_settings.dpcd_lane_settings);
- link_training_settings.allow_invalid_msa_timing_param = false;
/*Usage: Measure DP physical lane signal
* by DP SI test equipment automatically.
* PHY test pattern request is generated by equipment via HPD interrupt.
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h
b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 3fc868b19f2f..e94bcdb3e134 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -116,9 +116,13 @@ struct link_training_settings {
#endif
bool enhanced_framing;
- bool allow_invalid_msa_timing_param;
enum lttpr_mode lttpr_mode;
+ /* disallow different lanes to have different lane settings */
+ bool disallow_per_lane_settings;
+ /* dpcd lane settings will always use the same hw lane settings
+ * even if it doesn't match requested lane adjust */
+ bool always_match_dpcd_with_hw_lane_settings;
/*****************************************************************
* training states - parameters that can change in link training
--
2.25.1
