Since the EEPROM is specific to the device for each of these messages,
use the dev_* macro instead of DRM_* to make it easier to identify the
GPU that correlates to the EEPROM messages.
Signed-off-by: Kent Russell <kent.russ...@amd.com>
---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 40 +++++++++----------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 0428a1d3d22a..3792a69b876f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -201,9 +201,9 @@ static int __write_table_header(struct
amdgpu_ras_eeprom_control *control)
up_read(&adev->reset_sem);
if (res < 0) {
- DRM_ERROR("Failed to write EEPROM table header:%d", res);
+ dev_err(adev->dev, "Failed to write EEPROM table header:%d",
res);
} else if (res < RAS_TABLE_HEADER_SIZE) {
- DRM_ERROR("Short write:%d out of %d\n",
+ dev_err(adev->dev, "Short write:%d out of %d\n",
res, RAS_TABLE_HEADER_SIZE);
res = -EIO;
} else {
@@ -395,12 +395,12 @@ static int __amdgpu_ras_eeprom_write(struct
amdgpu_ras_eeprom_control *control,
buf, buf_size);
up_read(&adev->reset_sem);
if (res < 0) {
- DRM_ERROR("Writing %d EEPROM table records error:%d",
+ dev_err(adev->dev, "Writing %d EEPROM table records error:%d",
num, res);
} else if (res < buf_size) {
/* Short write, return error.
*/
- DRM_ERROR("Wrote %d records out of %d",
+ dev_err(adev->dev, "Wrote %d records out of %d",
res / RAS_TABLE_RECORD_SIZE, num);
res = -EIO;
} else {
@@ -541,7 +541,7 @@ amdgpu_ras_eeprom_update_header(struct
amdgpu_ras_eeprom_control *control)
buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
if (!buf) {
- DRM_ERROR("allocating memory for table of size %d bytes
failed\n",
+ dev_err(adev->dev, "allocating memory for table of size %d
bytes failed\n",
control->tbl_hdr.tbl_size);
res = -ENOMEM;
goto Out;
@@ -554,11 +554,11 @@ amdgpu_ras_eeprom_update_header(struct
amdgpu_ras_eeprom_control *control)
buf, buf_size);
up_read(&adev->reset_sem);
if (res < 0) {
- DRM_ERROR("EEPROM failed reading records:%d\n",
+ dev_err(adev->dev, "EEPROM failed reading records:%d\n",
res);
goto Out;
} else if (res < buf_size) {
- DRM_ERROR("EEPROM read %d out of %d bytes\n",
+ dev_err(adev->dev, "EEPROM read %d out of %d bytes\n",
res, buf_size);
res = -EIO;
goto Out;
@@ -604,10 +604,10 @@ int amdgpu_ras_eeprom_append(struct
amdgpu_ras_eeprom_control *control,
return 0;
if (num == 0) {
- DRM_ERROR("will not append 0 records\n");
+ dev_err(adev->dev, "will not append 0 records\n");
return -EINVAL;
} else if (num > control->ras_max_record_count) {
- DRM_ERROR("cannot append %d records than the size of table
%d\n",
+ dev_err(adev->dev, "cannot append %d records than the size of
table %d\n",
num, control->ras_max_record_count);
return -EINVAL;
}
@@ -650,12 +650,12 @@ static int __amdgpu_ras_eeprom_read(struct
amdgpu_ras_eeprom_control *control,
buf, buf_size);
up_read(&adev->reset_sem);
if (res < 0) {
- DRM_ERROR("Reading %d EEPROM table records error:%d",
+ dev_err(adev->dev, "Reading %d EEPROM table records error:%d",
num, res);
} else if (res < buf_size) {
/* Short read, return error.
*/
- DRM_ERROR("Read %d records out of %d",
+ dev_err(adev->dev, "Read %d records out of %d",
res / RAS_TABLE_RECORD_SIZE, num);
res = -EIO;
} else {
@@ -689,10 +689,10 @@ int amdgpu_ras_eeprom_read(struct
amdgpu_ras_eeprom_control *control,
return 0;
if (num == 0) {
- DRM_ERROR("will not read 0 records\n");
+ dev_err(adev->dev, "will not read 0 records\n");
return -EINVAL;
} else if (num > control->ras_num_recs) {
- DRM_ERROR("too many records to read:%d available:%d\n",
+ dev_err(adev->dev, "too many records to read:%d available:%d\n",
num, control->ras_num_recs);
return -EINVAL;
}
@@ -1005,7 +1005,7 @@ static int __verify_ras_table_checksum(struct
amdgpu_ras_eeprom_control *control
control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
buf = kzalloc(buf_size, GFP_KERNEL);
if (!buf) {
- DRM_ERROR("Out of memory checking RAS table checksum.\n");
+ dev_err(adev->dev, "Out of memory checking RAS table
checksum.\n");
return -ENOMEM;
}
@@ -1014,7 +1014,7 @@ static int __verify_ras_table_checksum(struct
amdgpu_ras_eeprom_control *control
control->ras_header_offset,
buf, buf_size);
if (res < buf_size) {
- DRM_ERROR("Partial read for checksum, res:%d\n", res);
+ dev_err(adev->dev, "Partial read for checksum, res:%d\n", res);
/* On partial reads, return -EIO.
*/
if (res >= 0)
@@ -1061,7 +1061,7 @@ int amdgpu_ras_eeprom_init(struct
amdgpu_ras_eeprom_control *control,
control->i2c_address +
control->ras_header_offset,
buf, RAS_TABLE_HEADER_SIZE);
if (res < RAS_TABLE_HEADER_SIZE) {
- DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
+ dev_err(adev->dev, "Failed to read EEPROM table header,
res:%d", res);
return res >= 0 ? -EIO : res;
}
@@ -1071,11 +1071,11 @@ int amdgpu_ras_eeprom_init(struct
amdgpu_ras_eeprom_control *control,
control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
if (hdr->header == RAS_TABLE_HDR_VAL) {
- DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
+ dev_dbg(adev->dev, "Found existing EEPROM table with %d
records",
control->ras_num_recs);
res = __verify_ras_table_checksum(control);
if (res)
- DRM_ERROR("RAS table incorrect checksum or error:%d\n",
+ dev_err(adev->dev, "RAS table incorrect checksum or
error:%d\n",
res);
/* Warn if we are at 90% of the threshold or above
@@ -1088,7 +1088,7 @@ int amdgpu_ras_eeprom_init(struct
amdgpu_ras_eeprom_control *control,
amdgpu_bad_page_threshold != 0) {
res = __verify_ras_table_checksum(control);
if (res)
- DRM_ERROR("RAS Table incorrect checksum or error:%d\n",
+ dev_err(adev->dev, "RAS Table incorrect checksum or
error:%d\n",
res);
if (ras->bad_page_cnt_threshold > control->ras_num_recs) {
/* This means that, the threshold was increased since
@@ -1116,7 +1116,7 @@ int amdgpu_ras_eeprom_init(struct
amdgpu_ras_eeprom_control *control,
}
}
} else {
- DRM_INFO("Creating a new EEPROM table");
+ dev_info(adev->dev, "Creating a new EEPROM table");
res = amdgpu_ras_eeprom_reset_table(control);
}
--
2.25.1
