[AMD Official Use Only]
Reviewed-by: David Nieto <david.ni...@amd.com>
________________________________
From: Skvortsov, Victor <victor.skvort...@amd.com>
Sent: Thursday, December 16, 2021 11:42 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Deng, Emily
<emily.d...@amd.com>; Liu, Monk <monk....@amd.com>; Ming, Davis
<davis.m...@amd.com>; Liu, Shaoyun <shaoyun....@amd.com>; Zhou, Peng Ju
<pengju.z...@amd.com>; Chen, JingWen <jingwen.ch...@amd.com>; Chen, Horace
<horace.c...@amd.com>; Nieto, David M <david.ni...@amd.com>
Cc: Skvortsov, Victor <victor.skvort...@amd.com>
Subject: [PATCH v3 1/5] drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions
Add helper macros to change register access
from direct to indirect.
Signed-off-by: Victor Skvortsov <victor.skvort...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 8a9ca87d8663..473767e03676 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -51,6 +51,8 @@
#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)
+#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg,
AMDGPU_REGS_NO_KIQ, ip##_HWIP)
+
#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
+ reg, \
AMDGPU_REGS_NO_KIQ, ip##_HWIP)
@@ -65,6 +67,9 @@
#define WREG32_SOC15_IP(ip, reg, value) \
__WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
+#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
+ __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
+
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
+ reg, \
value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
--
2.25.1
