Change-Id: Ic2a488ee253a913d806bd33ee9c90e31a71af320
Signed-off-by: Stanley.Yang <stanley.y...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 23 -----------------------
drivers/gpu/drm/amd/amdgpu/umc_v8_7.c | 6 ------
2 files changed, 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 6953426f0bed..526de1ca9b8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -61,22 +61,9 @@ static void
umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device
uint32_t channel_index,
unsigned long *error_count)
{
- uint32_t ecc_err_cnt;
uint64_t mc_umc_status;
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
- /*
- * select the lower chip and check the error count
- * skip add error count, calc error counter only from mca_umc_status
- */
- ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_lo_chip;
-
- /*
- * select the higher chip and check the err counter
- * skip add error count, calc error counter only from mca_umc_status
- */
- ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_hi_chip;
-
/* check for SRAM correctable error
MCUMC_STATUS is a 64 bit register */
mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;
@@ -110,15 +97,11 @@ static void umc_v6_7_ecc_info_query_ras_error_count(struct
amdgpu_device *adev,
uint32_t umc_inst = 0;
uint32_t ch_inst = 0;
- uint32_t umc_reg_offset = 0;
uint32_t channel_index = 0;
/*TODO: driver needs to toggle DF Cstate to ensure
* safe access of UMC registers. Will add the protection */
LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
- umc_reg_offset = get_umc_v6_7_reg_offset(adev,
- umc_inst,
- ch_inst);
channel_index = get_umc_v6_7_channel_index(adev,
umc_inst,
ch_inst);
@@ -133,7 +116,6 @@ static void umc_v6_7_ecc_info_query_ras_error_count(struct
amdgpu_device *adev,
static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
struct ras_err_data *err_data,
- uint32_t umc_reg_offset,
uint32_t ch_inst,
uint32_t umc_inst)
{
@@ -192,18 +174,13 @@ static void
umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev
uint32_t umc_inst = 0;
uint32_t ch_inst = 0;
- uint32_t umc_reg_offset = 0;
/*TODO: driver needs to toggle DF Cstate to ensure
* safe access of UMC resgisters. Will add the protection
* when firmware interface is ready */
LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
- umc_reg_offset = get_umc_v6_7_reg_offset(adev,
- umc_inst,
- ch_inst);
umc_v6_7_ecc_info_query_error_address(adev,
err_data,
- umc_reg_offset,
ch_inst,
umc_inst);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
index 05f79eea307c..cd57f39df7d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
@@ -114,7 +114,6 @@ static void umc_v8_7_ecc_info_query_ras_error_count(struct
amdgpu_device *adev,
static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
struct ras_err_data *err_data,
- uint32_t umc_reg_offset,
uint32_t ch_inst,
uint32_t umc_inst)
{
@@ -173,19 +172,14 @@ static void
umc_v8_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev
uint32_t umc_inst = 0;
uint32_t ch_inst = 0;
- uint32_t umc_reg_offset = 0;
/* TODO: driver needs to toggle DF Cstate to ensure
* safe access of UMC resgisters. Will add the protection
* when firmware interface is ready
*/
LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
- umc_reg_offset = get_umc_v8_7_reg_offset(adev,
- umc_inst,
- ch_inst);
umc_v8_7_ecc_info_query_error_address(adev,
err_data,
- umc_reg_offset,
ch_inst,
umc_inst);
}
--
2.17.1
