[PATCH 29/43] drm/amd/display: Disable DTB Ref Clock Switching in dcn32

[Alex Deucher]

From: Dillon Varone <dillon.var...@amd.com>

[How & Why]
To be enabled once PMFW supports it.

Signed-off-by: Dillon Varone <dillon.var...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++++
 drivers/gpu/drm/amd/display/dc/dc.h                          | 1 -
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 774de29fa532..f147c65137c6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -607,6 +607,10 @@ void dcn32_clk_mgr_construct(
        if (clk_mgr->base.dentist_vco_freq_khz == 0)
                clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per 
HW docs */
 
+       if (clk_mgr->dccg->ref_dtbclk_khz != 
clk_mgr->base.boot_snapshot.dtbclk) {
+               clk_mgr->dccg->ref_dtbclk_khz = 
clk_mgr->base.boot_snapshot.dtbclk;
+       }
+
        if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
                //ASSERT(clk_mgr->base.dprefclk_khz == 
clk_mgr->base.boot_snapshot.dprefclk);
                //clk_mgr->base.dprefclk_khz = 
clk_mgr->base.boot_snapshot.dprefclk;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index b6decdf820fa..e25e91bfe763 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -430,7 +430,6 @@ struct dc_clocks {
        bool p_state_change_support;
        enum dcn_zstate_support_state zstate_support;
        bool dtbclk_en;
-       int dtbclk_khz;
        bool fclk_p_state_change_support;
        enum dcn_pwr_state pwr_state;
        /*
-- 
2.35.3