The function dcn32_helper_populate_phantom_dlg_params uses FPU
operations. For this reason, this commit moves this function to the
dcn32_fpu file, and we ensure that we only invoke it under the
kernel_fpu protection.
Reviewed-by: Harry Wentland <harry.wentl...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 7 +++
.../display/dc/dcn32/dcn32_resource_helpers.c | 44 -------------------
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 43 ++++++++++++++++++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.h | 5 +++
4 files changed, 55 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 39214a0dcdf2..411ce13847c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -88,6 +88,7 @@
#include "dml/dcn30/display_mode_vba_30.h"
#include "vm_helper.h"
#include "dcn20/dcn20_vmid.h"
+#include "dml/dcn32/dcn32_fpu.h"
#define DCN_BASE__INST0_SEG1 0x000000C0
#define DCN_BASE__INST0_SEG2 0x000034C0
@@ -312,6 +313,7 @@ enum dcn32_clk_src_array_id {
.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
regBIF_BX0_ ## reg_name
+#undef CTX
#define CTX ctx
#define REG(reg_name) \
(DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ##
reg_name)
@@ -2667,6 +2669,11 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
memset(merge, 0, MAX_PIPES * sizeof(bool));
*vlevel = dcn20_validate_apply_pipe_split_flags(dc,
context, *vlevel, split, merge);
+ // Most populate phantom DLG params before programming
hardware / timing for phantom pipe
+ DC_FP_START();
+ dcn32_helper_populate_phantom_dlg_params(dc, context,
pipes, *pipe_cnt);
+ DC_FP_END();
+
// Note: We can't apply the phantom pipes to hardware
at this time. We have to wait
// until driver has acquired the DMCUB lock to do it
safely.
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index a6ef1dba01fe..633d3ee18cfa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -28,50 +28,6 @@
#include "dcn20/dcn20_resource.h"
#include "dml/dcn32/display_mode_vba_util_32.h"
-/**
- *
********************************************************************************************
- * dcn32_helper_populate_phantom_dlg_params: Get DLG params for phantom pipes
and populate pipe_ctx
- * with those params.
- *
- * This function must be called AFTER the phantom pipes are added to context
and run through DML
- * (so that the DLG params for the phantom pipes can be populated), and BEFORE
we program the
- * timing for the phantom pipes.
- *
- * @param [in] dc: current dc state
- * @param [in] context: new dc state
- * @param [in] pipes: DML pipe params array
- * @param [in] pipe_cnt: DML pipe count
- *
- * @return: void
- *
- *
********************************************************************************************
- */
-void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
- struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt)
-{
- uint32_t i, pipe_idx;
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- if (!pipe->stream)
- continue;
-
- if (pipe->plane_state && pipe->stream->mall_stream_config.type
== SUBVP_PHANTOM) {
- pipes[pipe_idx].pipe.dest.vstartup_start =
get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
- pipe_idx);
- pipes[pipe_idx].pipe.dest.vupdate_offset =
get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
- pipe_idx);
- pipes[pipe_idx].pipe.dest.vupdate_width =
get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
- pipe_idx);
- pipes[pipe_idx].pipe.dest.vready_offset =
get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
- pipe_idx);
- pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
- }
- pipe_idx++;
- }
-}
-
/**
*
********************************************************************************************
* dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways needed
for SubVP
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 89b596599c3d..253ff9659b0d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -111,3 +111,46 @@ void dcn32_build_wm_range_table_fpu(struct
clk_mgr_internal *clk_mgr)
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk =
0xFFFF;
}
+/**
+ * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
+ * and populate pipe_ctx with those params.
+ *
+ * This function must be called AFTER the phantom pipes are added to context
+ * and run through DML (so that the DLG params for the phantom pipes can be
+ * populated), and BEFORE we program the timing for the phantom pipes.
+ *
+ * @dc: [in] current dc state
+ * @context: [in] new dc state
+ * @pipes: [in] DML pipe params array
+ * @pipe_cnt: [in] DML pipe count
+ */
+void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
+ struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt)
+{
+ uint32_t i, pipe_idx;
+
+ dc_assert_fp_enabled();
+
+ for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe->stream)
+ continue;
+
+ if (pipe->plane_state && pipe->stream->mall_stream_config.type
== SUBVP_PHANTOM) {
+ pipes[pipe_idx].pipe.dest.vstartup_start =
+ get_vstartup(&context->bw_ctx.dml, pipes,
pipe_cnt, pipe_idx);
+ pipes[pipe_idx].pipe.dest.vupdate_offset =
+ get_vupdate_offset(&context->bw_ctx.dml, pipes,
pipe_cnt, pipe_idx);
+ pipes[pipe_idx].pipe.dest.vupdate_width =
+ get_vupdate_width(&context->bw_ctx.dml, pipes,
pipe_cnt, pipe_idx);
+ pipes[pipe_idx].pipe.dest.vready_offset =
+ get_vready_offset(&context->bw_ctx.dml, pipes,
pipe_cnt, pipe_idx);
+ pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+ }
+ pipe_idx++;
+ }
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
index 72a6dd75af0e..492f99b6d561 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
@@ -31,4 +31,9 @@
void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr);
+void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
+ struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt);
+
#endif
--
2.37.0
