From: "Lee, Alvin" <alvin.l...@amd.com>
[Description]
In some cases the viewport position of the
main pipes can change without triggering a full update.
In this case the subvp phantom viewports must be updated accordingly.
Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Pavle Kotarac <pavle.kota...@amd.com>
Signed-off-by: Alvin Lee <alvin.l...@amd.com>
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 ++--
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c | 32 +++++++++++++++++++
.../drm/amd/display/dc/dcn32/dcn32_hwseq.h | 4 +++
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 +++
5 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6271caca4d9a..6f8c344e321d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1898,8 +1898,11 @@ void dcn20_post_unlock_program_front_end(
* can underflow due to HUBP_VTG_SEL programming if
done in the regular front end
* programming sequence).
*/
- if (pipe->stream &&
pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
- dcn20_program_pipe(dc, pipe, context);
+ if (pipe->stream &&
pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+ if (dc->hwss.update_phantom_vp_position)
+ dc->hwss.update_phantom_vp_position(dc,
context, pipe);
+ dcn20_program_pipe(dc, pipe, context);
+ }
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index dbf2d7cc96c5..449459ca5a72 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1301,3 +1301,35 @@ void dcn32_update_phy_state(struct dc_state *state,
struct pipe_ctx *pipe_ctx,
} else
BREAK_TO_DEBUGGER();
}
+
+/* For SubVP the main pipe can have a viewport position change
+ * without a full update. In this case we must also update the
+ * viewport positions for the phantom pipe accordingly.
+ */
+void dcn32_update_phantom_vp_position(struct dc *dc,
+ struct dc_state *context,
+ struct pipe_ctx *phantom_pipe)
+{
+ uint8_t i;
+ struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (pipe->stream && pipe->stream->mall_stream_config.type ==
SUBVP_MAIN &&
+ pipe->stream->mall_stream_config.paired_stream
== phantom_pipe->stream) {
+ if (pipe->plane_state &&
pipe->plane_state->update_flags.bits.position_change) {
+
+ phantom_plane->src_rect.x =
pipe->plane_state->src_rect.x;
+ phantom_plane->src_rect.y =
pipe->plane_state->src_rect.y;
+ phantom_plane->clip_rect.x =
pipe->plane_state->clip_rect.x;
+ phantom_plane->dst_rect.x =
pipe->plane_state->dst_rect.x;
+ phantom_plane->dst_rect.y =
pipe->plane_state->dst_rect.y;
+
+
phantom_pipe->plane_state->update_flags.bits.position_change = 1;
+ resource_build_scaling_params(phantom_pipe);
+ return;
+ }
+ }
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
index 221e31144d50..150d541f35b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -87,4 +87,8 @@ bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx
*pipe_ctx);
void dcn32_update_phy_state(struct dc_state *state, struct pipe_ctx *pipe_ctx,
enum phy_state target_state);
+void dcn32_update_phantom_vp_position(struct dc *dc,
+ struct dc_state *context,
+ struct pipe_ctx *phantom_pipe);
+
#endif /* __DC_HWSS_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 28d220218133..c554929471af 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -105,6 +105,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,
.update_visual_confirm_color = dcn20_update_visual_confirm_color,
.update_phy_state = dcn32_update_phy_state,
+ .update_phantom_vp_position = dcn32_update_phantom_vp_position,
};
static const struct hwseq_private_funcs dcn32_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 52b4350c9cd8..d7a7b2790143 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -247,6 +247,11 @@ struct hw_sequencer_funcs {
void (*update_phy_state)(struct dc_state *state, struct pipe_ctx
*pipe_ctx, enum phy_state target_state);
+
+ void (*update_phantom_vp_position)(struct dc *dc,
+ struct dc_state *context,
+ struct pipe_ctx *phantom_pipe);
+
void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);
void (*subvp_pipe_control_lock)(struct dc *dc,
struct dc_state *context,
--
2.34.1
