[PATCH] drm/amdgpu: Enable F32_WPTR_POLL_ENABLE in mqd

[Ji, Ruili]

From: Ruili Ji <ruili...@amd.com>

This patch is to fix the SDMA user queue doorbell missing issue on
SDMA 6.0. F32_WPTR_POLL_ENABLE has to be set if doorbell mode is used.
Otherwise ringing SDMA user queue doorbell can't wake up system from gfxoff.

Signed-off-by: Yifan Zhang <yifan1.zh...@amd.com>
Signed-off-by: Ruili Ji <ruili...@amd.com>
Change-Id: Icfb97c3551509b4d7fb172ebc4200edf5844e5e1
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c           | 3 ++-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index db51230163c5..0150f66a5ae6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -846,7 +846,8 @@ static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, 
void *mqd,
        m->sdmax_rlcx_rb_cntl =
                order_base_2(prop->queue_size / 4) << 
SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
                1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
-               4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
+               4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
+               1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
 
        m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
        m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 26b53b6d673e..4f6390f3236e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -333,7 +333,8 @@ static void update_mqd_sdma(struct mqd_manager *mm, void 
*mqd,
                << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
                q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT |
                1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
-               6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
+               6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
+               1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
 
        m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
        m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
-- 
2.25.1