From: Alvin Lee <alvin.l...@amd.com>
[ Upstream commit c3d3f35b725bf9c93bec6d3c056f6bb7cfd27403 ]
Missed enabling timing sync on DCN32 because DCN32 has a different DML
param.
Tested-by: Mark Broadworth <mark.broadwo...@amd.com>
Reviewed-by: Martin Leung <martin.le...@amd.com>
Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Alvin Lee <alvin.l...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index d34e0f1314d9..bc4f48ea8d4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1228,6 +1228,7 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.dcc = false;
pipes[pipe_cnt].pipe.src.dcc_rate = 1;
pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes =
synchronized_vblank;
+ pipes[pipe_cnt].pipe.dest.synchronize_timings =
synchronized_vblank;
pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total -
timing->h_front_porch;
pipes[pipe_cnt].pipe.dest.hblank_end =
pipes[pipe_cnt].pipe.dest.hblank_start
- timing->h_addressable
--
2.35.1
