It was reported that on kernel v6.2-rc1, we have the following stack size issue:
make[3]: *** [/kisskb/src/scripts/Makefile.build:504: drivers/media] Error 2 [...]/display/dc/dml/dcn31/display_mode_vba_31.c: In function 'UseMinimumDCFCLK': [...]/display/dc/dml/dcn31/display_mode_vba_31.c:7082:1: error: the frame size of 2224 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] This commit move the array of doubles DynamicMetadataVMExtraLatency to a separated struct (UseMinimumDCFCLK_vars) to reduce the stack size. Cc: Alex Deucher <alexdeuc...@gmail.com> Cc: Aurabindo Pillai <aurabindo.pil...@amd.com> Cc: Hamza Mahfooz <hamza.mahf...@amd.com> Cc: Roman Li <roman...@amd.com> Cc: Geert Uytterhoeven <ge...@linux-m68k.org> Link: https://lore.kernel.org/all/20221227082932.798359-1-ge...@linux-m68k.org/ Reported-by: Geert Uytterhoeven <ge...@linux-m68k.org> Signed-off-by: Rodrigo Siqueira <rodrigo.sique...@amd.com> --- .../drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 9 ++++----- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 + 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 8175f3603f00..904703353958 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -6932,7 +6932,6 @@ static void UseMinimumDCFCLK( NormalEfficiency = v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0; for (i = 0; i < v->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { - double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX]; double MinimumTWait; double NonDPTEBandwidth; double DPTEBandwidth; @@ -6992,14 +6991,14 @@ static void UseMinimumDCFCLK( v->UseMinimumDCFCLK_stack_reduction.PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k]; ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k]) / (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]); - DynamicMetadataVMExtraLatency[k] = + v->UseMinimumDCFCLK_stack_reduction.DynamicMetadataVMExtraLatency[k] = (v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ? v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0; PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - v->UrgLatency[i] * ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels : v->GPUVMMaxPageTableLevels - 2) * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - - DynamicMetadataVMExtraLatency[k]; + - v->UseMinimumDCFCLK_stack_reduction.DynamicMetadataVMExtraLatency[k]; if (PrefetchTime > 0) { double ExpectedVRatioPrefetch; @@ -7041,7 +7040,7 @@ static void UseMinimumDCFCLK( &dummy2, &dummy3); AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe - - TdmsksPipe - DynamicMetadataVMExtraLatency[k]; + - TdmsksPipe - v->UseMinimumDCFCLK_stack_reduction.DynamicMetadataVMExtraLatency[k]; if (AllowedTimeForUrgentExtraLatency > 0) { v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max( v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k], @@ -7062,7 +7061,7 @@ static void UseMinimumDCFCLK( 0); for (k = 0; k < v->NumberOfActivePlanes; ++k) { double MaximumTvmPlus2Tr0PlusTsw; - MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k]; + MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - v->UseMinimumDCFCLK_stack_reduction.DynamicMetadataVMExtraLatency[k]; if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + v->UseMinimumDCFCLK_stack_reduction.PrefetchPixelLinesTime[k] / 4) { DCFCLKRequiredForPeakBandwidth = v->DCFCLKPerState[i]; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 4c5206bfad38..01c767f08b38 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -254,6 +254,7 @@ struct UseMinimumDCFCLK_vars { double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX]; double PrefetchPixelLinesTime[DC__NUM_DPP__MAX]; double DCFCLKRequiredForPeakBandwidthPerPlane[DC__NUM_DPP__MAX]; + double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX]; }; struct dummy_vars { -- 2.39.0
