[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>
Regards,
Hawking
From: Yifan Zha <yifan....@amd.com>
Date: Wednesday, February 1, 2023 at 13:15
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>, Deucher,
Alexander <alexander.deuc...@amd.com>, Zhang, Hawking <hawking.zh...@amd.com>
Cc: Chen, Horace <horace.c...@amd.com>, Chang, HaiJun <haijun.ch...@amd.com>,
Zha, YiFan(Even) <yifan....@amd.com>
Subject: [PATCH v2] drm/amdgpu: Remove writing GRBM_GFX_CNTL in RLCG interface
under SRIOV
[Why]
Accessing GRBM_GFX_CNTL in full access time has risk when VF is doing MMIO
attacking.
Therefore, VF writing GRBM_GFX_CNTL are blocked by L1 Policy.
For RLCG interface, RLCG use SCRATCH_REG2 which is copied from GRBM_GFX_CNTL.
[How]
Remove writing GRBM_GFX_CNTL in amdgpu_virt_rlcg_reg_rw.
v2:
Remove directly writing GRBM_GFX_INDEX in amdgpu_virt_rlcg_reg_rw
as RLCG interface no need to use it.
Signed-off-by: Yifan Zha <yifan....@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index f39391e03d46..ca5a1d026f5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -983,11 +983,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device
*adev, u32 offset, u32 v
if (offset == reg_access_ctrl->grbm_cntl) {
/* if the target reg offset is grbm_cntl, write to
scratch_reg2 */
writel(v, scratch_reg2);
- writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
} else if (offset == reg_access_ctrl->grbm_idx) {
/* if the target reg offset is grbm_idx, write to scratch_reg3
*/
writel(v, scratch_reg3);
- writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
} else {
/*
* SCRATCH_REG0 = read/write value
--
2.25.1
