Am 03.02.23 um 20:08 schrieb Shashank Sharma:
From: Alex Deucher <alexander.deuc...@amd.com>

This patch initializes doorbell pool with bar manager, which will
divide all the doorbell memory into pages.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Shashank Sharma <shashank.sha...@amd.com>
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 +++++++++++
  1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e04409210415..95017de6b23d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1837,6 +1837,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        if (r)
                return r;
+ /* Initialize DOORBELL pool with all of DOORBELL divided into pages */
+       r = amdgpu_bar_mgr_init(adev, AMDGPU_PL_DOORBELL);

Just replacing this with ttm_range_man_init() should be sufficient to not use the VRAM manager here.

Christian.

+       if (r) {
+               DRM_ERROR("Failed initializing DOORBELL heap.\n");
+               return r;
+       }
+
        /*
         *The reserved vram for firmware must be pinned to the specified
         *place on the VRAM, so reserve it early.
@@ -1890,6 +1897,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
                 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
+ DRM_INFO("amdgpu: %uM of DOORBELL memory ready\n",
+                (unsigned) (adev->gmc.doorbell_aper_size / (1024 * 1024)));
+
        /* Compute GTT size, either based on 1/2 the size of RAM size
         * or whatever the user passed on module init */
        if (amdgpu_gtt_size == -1) {
@@ -1991,6 +2001,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
        }
amdgpu_bar_mgr_fini(adev, TTM_PL_VRAM);
+       amdgpu_bar_mgr_fini(adev, AMDGPU_PL_DOORBELL);
        amdgpu_gtt_mgr_fini(adev);
        amdgpu_preempt_mgr_fini(adev);
        ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);

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