Re: [PATCH v4 1/3] drm/amdgpu: Increase GFX6 graphics ring size.

[Christian König]

Am 13.04.23 um 16:22 schrieb Bas Nieuwenhuizen:
To ensure it supports 192 IBs per submission, so we can keep a
simplified IB limit in the follow up patch without having to
look at IP or GPU version.
Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

I've took the time and double checked the docs and the maximum size of 
the ring buffer on GFX6 is indeed only 1MiB.

So even with this change sched_hw_submission can still go as high as 512 
without problems (the default is 2 or 4 IIRC).

Reviewed-by: Christian König <christian.koe...@amd.com>

---
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index c41219e23151..d9ce4d1c50e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3073,7 +3073,7 @@ static int gfx_v6_0_sw_init(void *handle)
                ring = &adev->gfx.gfx_ring[i];
                ring->ring_obj = NULL;
                sprintf(ring->name, "gfx");
-               r = amdgpu_ring_init(adev, ring, 1024,
+               r = amdgpu_ring_init(adev, ring, 2048,
                                     &adev->gfx.eop_irq,
                                     AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
                                     AMDGPU_RING_PRIO_DEFAULT, NULL);