Some ASICs support fatal error event but do not
support pcie_bif ras.

Signed-off-by: Candice Li <candice...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 3ab8a88789c8fe..22f401fd1901cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1597,8 +1597,7 @@ static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
 {
        /* Fatal error events are handled on host side */
-       if (amdgpu_sriov_vf(adev) ||
-               !amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF))
+       if (amdgpu_sriov_vf(adev))
                return;
 
        if (adev->nbio.ras &&
-- 
2.17.1

Reply via email to