The extra legacy TLB flush mitigation is only required on rev0.
Signed-off-by: Graham Sider <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 38e4828f574e..ba8251b6b279 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -844,11 +844,8 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
} else if (flush_type == 2 &&
- adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) {
- /* FIXME: Temporarily add a legacy flush (type 0) before
heavyweight
- * flush for gfx943 to mitigate a bug which causes CPC UTCL1 to
return
- * stale translations even after TLB heavyweight flush.
- */
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) &&
+ adev->rev_id == 0) {
inv_req = gmc_v9_0_get_invalidate_req(vmid, 0);
inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
} else {
@@ -993,11 +990,9 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct
amdgpu_device *adev,
kiq->pmf->kiq_invalidate_tlbs(ring,
pasid, 2, all_hub);
- /* FIXME: Temporarily add a legacy flush (type 0) before
heavyweight
- * flush for gfx943 to mitigate a bug which causes CPC UTCL1 to
return
- * stale translations even after TLB heavyweight flush.
- */
- if (flush_type == 2 && adev->ip_versions[GC_HWIP][0] ==
IP_VERSION(9, 4, 3))
+ if (flush_type == 2 &&
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) &&
+ adev->rev_id == 0)
kiq->pmf->kiq_invalidate_tlbs(ring,
pasid, 0, all_hub);
--
2.25.1
